1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "arch/kernel_stats.hh"
32#include "base/output.hh"
33#include "cpu/base.hh"
34#include "cpu/profile.hh"
35#include "cpu/quiesce_event.hh"
36#include "cpu/thread_state.hh"
37#include "mem/fs_translating_port_proxy.hh"
38#include "mem/port.hh"
39#include "mem/port_proxy.hh"
40#include "mem/se_translating_port_proxy.hh"
41#include "sim/full_system.hh"
42#include "sim/serialize.hh"
43#include "sim/system.hh"
44
45ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "arch/kernel_stats.hh"
32#include "base/output.hh"
33#include "cpu/base.hh"
34#include "cpu/profile.hh"
35#include "cpu/quiesce_event.hh"
36#include "cpu/thread_state.hh"
37#include "mem/fs_translating_port_proxy.hh"
38#include "mem/port.hh"
39#include "mem/port_proxy.hh"
40#include "mem/se_translating_port_proxy.hh"
41#include "sim/full_system.hh"
42#include "sim/serialize.hh"
43#include "sim/system.hh"
44
45ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
|
46 : numInst(0), numOp(0), numLoad(0), _status(ThreadContext::Halted),
47 baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
| 46 : numInst(0), numOp(0), numLoad(0), startNumLoad(0),
47 _status(ThreadContext::Halted), baseCpu(cpu),
48 _contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0),
|
48 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
49 kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL),
50 proxy(NULL), funcExeInst(0), storeCondFailures(0)
51{
52}
53
54ThreadState::~ThreadState()
55{
56 if (physProxy != NULL)
57 delete physProxy;
58 if (virtProxy != NULL)
59 delete virtProxy;
60 if (proxy != NULL)
61 delete proxy;
62}
63
64void
65ThreadState::serialize(std::ostream &os)
66{
67 SERIALIZE_ENUM(_status);
68 // thread_num and cpu_id are deterministic from the config
69 SERIALIZE_SCALAR(funcExeInst);
70
71 if (!FullSystem)
72 return;
73
74 Tick quiesceEndTick = 0;
75 if (quiesceEvent->scheduled())
76 quiesceEndTick = quiesceEvent->when();
77 SERIALIZE_SCALAR(quiesceEndTick);
78 if (kernelStats)
79 kernelStats->serialize(os);
80}
81
82void
83ThreadState::unserialize(Checkpoint *cp, const std::string §ion)
84{
85
86 UNSERIALIZE_ENUM(_status);
87 // thread_num and cpu_id are deterministic from the config
88 UNSERIALIZE_SCALAR(funcExeInst);
89
90 if (!FullSystem)
91 return;
92
93 Tick quiesceEndTick;
94 UNSERIALIZE_SCALAR(quiesceEndTick);
95 if (quiesceEndTick)
96 baseCpu->schedule(quiesceEvent, quiesceEndTick);
97 if (kernelStats)
98 kernelStats->unserialize(cp, section);
99}
100
101void
102ThreadState::initMemProxies(ThreadContext *tc)
103{
104 // The port proxies only refer to the data port on the CPU side
105 // and can safely be done at init() time even if the CPU is not
106 // connected, i.e. when restoring from a checkpoint and later
107 // switching the CPU in.
108 if (FullSystem) {
109 assert(physProxy == NULL);
110 // This cannot be done in the constructor as the thread state
111 // itself is created in the base cpu constructor and the
112 // getDataPort is a virtual function
113 physProxy = new PortProxy(baseCpu->getDataPort(),
114 baseCpu->cacheLineSize());
115
116 assert(virtProxy == NULL);
117 virtProxy = new FSTranslatingPortProxy(tc);
118 } else {
119 assert(proxy == NULL);
120 proxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
121 process,
122 SETranslatingPortProxy::NextPage);
123 }
124}
125
126PortProxy &
127ThreadState::getPhysProxy()
128{
129 assert(FullSystem);
130 assert(physProxy != NULL);
131 return *physProxy;
132}
133
134FSTranslatingPortProxy &
135ThreadState::getVirtProxy()
136{
137 assert(FullSystem);
138 assert(virtProxy != NULL);
139 return *virtProxy;
140}
141
142SETranslatingPortProxy &
143ThreadState::getMemProxy()
144{
145 assert(!FullSystem);
146 assert(proxy != NULL);
147 return *proxy;
148}
149
150void
151ThreadState::profileClear()
152{
153 if (profile)
154 profile->clear();
155}
156
157void
158ThreadState::profileSample()
159{
160 if (profile)
161 profile->sample(profileNode, profilePC);
162}
| 49 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
50 kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL),
51 proxy(NULL), funcExeInst(0), storeCondFailures(0)
52{
53}
54
55ThreadState::~ThreadState()
56{
57 if (physProxy != NULL)
58 delete physProxy;
59 if (virtProxy != NULL)
60 delete virtProxy;
61 if (proxy != NULL)
62 delete proxy;
63}
64
65void
66ThreadState::serialize(std::ostream &os)
67{
68 SERIALIZE_ENUM(_status);
69 // thread_num and cpu_id are deterministic from the config
70 SERIALIZE_SCALAR(funcExeInst);
71
72 if (!FullSystem)
73 return;
74
75 Tick quiesceEndTick = 0;
76 if (quiesceEvent->scheduled())
77 quiesceEndTick = quiesceEvent->when();
78 SERIALIZE_SCALAR(quiesceEndTick);
79 if (kernelStats)
80 kernelStats->serialize(os);
81}
82
83void
84ThreadState::unserialize(Checkpoint *cp, const std::string §ion)
85{
86
87 UNSERIALIZE_ENUM(_status);
88 // thread_num and cpu_id are deterministic from the config
89 UNSERIALIZE_SCALAR(funcExeInst);
90
91 if (!FullSystem)
92 return;
93
94 Tick quiesceEndTick;
95 UNSERIALIZE_SCALAR(quiesceEndTick);
96 if (quiesceEndTick)
97 baseCpu->schedule(quiesceEvent, quiesceEndTick);
98 if (kernelStats)
99 kernelStats->unserialize(cp, section);
100}
101
102void
103ThreadState::initMemProxies(ThreadContext *tc)
104{
105 // The port proxies only refer to the data port on the CPU side
106 // and can safely be done at init() time even if the CPU is not
107 // connected, i.e. when restoring from a checkpoint and later
108 // switching the CPU in.
109 if (FullSystem) {
110 assert(physProxy == NULL);
111 // This cannot be done in the constructor as the thread state
112 // itself is created in the base cpu constructor and the
113 // getDataPort is a virtual function
114 physProxy = new PortProxy(baseCpu->getDataPort(),
115 baseCpu->cacheLineSize());
116
117 assert(virtProxy == NULL);
118 virtProxy = new FSTranslatingPortProxy(tc);
119 } else {
120 assert(proxy == NULL);
121 proxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
122 process,
123 SETranslatingPortProxy::NextPage);
124 }
125}
126
127PortProxy &
128ThreadState::getPhysProxy()
129{
130 assert(FullSystem);
131 assert(physProxy != NULL);
132 return *physProxy;
133}
134
135FSTranslatingPortProxy &
136ThreadState::getVirtProxy()
137{
138 assert(FullSystem);
139 assert(virtProxy != NULL);
140 return *virtProxy;
141}
142
143SETranslatingPortProxy &
144ThreadState::getMemProxy()
145{
146 assert(!FullSystem);
147 assert(proxy != NULL);
148 return *proxy;
149}
150
151void
152ThreadState::profileClear()
153{
154 if (profile)
155 profile->clear();
156}
157
158void
159ThreadState::profileSample()
160{
161 if (profile)
162 profile->sample(profileNode, profilePC);
163}
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