1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "base/output.hh"
32#include "cpu/base.hh"
33#include "cpu/profile.hh"
34#include "cpu/thread_state.hh"
35#include "mem/port.hh"
36#include "mem/translating_port.hh"
37#include "mem/vport.hh"
38#include "sim/serialize.hh"
39
40#if FULL_SYSTEM
41#include "arch/kernel_stats.hh"
42#include "cpu/quiesce_event.hh"
43#endif
44
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "base/output.hh"
32#include "cpu/base.hh"
33#include "cpu/profile.hh"
34#include "cpu/thread_state.hh"
35#include "mem/port.hh"
36#include "mem/translating_port.hh"
37#include "mem/vport.hh"
38#include "sim/serialize.hh"
39
40#if FULL_SYSTEM
41#include "arch/kernel_stats.hh"
42#include "cpu/quiesce_event.hh"
43#endif
44
|
45#if FULL_SYSTEM
46ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid)
47#else
| |
48ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
| 45ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
|
49#endif
| |
50 : numInst(0), numLoad(0), _status(ThreadContext::Halted),
51 baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
52#if FULL_SYSTEM
53 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
54 kernelStats(NULL),
| 46 : numInst(0), numLoad(0), _status(ThreadContext::Halted),
47 baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
48#if FULL_SYSTEM
49 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
50 kernelStats(NULL),
|
55#else
56 process(_process),
| |
57#endif
| 51#endif
|
58 port(NULL), virtPort(NULL), physPort(NULL), funcExeInst(0),
59 storeCondFailures(0)
| 52 process(_process), port(NULL), virtPort(NULL), physPort(NULL),
53 funcExeInst(0), storeCondFailures(0)
|
60{
61}
62
63ThreadState::~ThreadState()
64{
| 54{
55}
56
57ThreadState::~ThreadState()
58{
|
65#if !FULL_SYSTEM
| |
66 if (port) {
67 delete port->getPeer();
68 delete port;
69 }
| 59 if (port) {
60 delete port->getPeer();
61 delete port;
62 }
|
70#endif
| |
71}
72
73void
74ThreadState::serialize(std::ostream &os)
75{
76 SERIALIZE_ENUM(_status);
77 // thread_num and cpu_id are deterministic from the config
78 SERIALIZE_SCALAR(funcExeInst);
79
80#if FULL_SYSTEM
81 Tick quiesceEndTick = 0;
82 if (quiesceEvent->scheduled())
83 quiesceEndTick = quiesceEvent->when();
84 SERIALIZE_SCALAR(quiesceEndTick);
85 if (kernelStats)
86 kernelStats->serialize(os);
87#endif
88}
89
90void
91ThreadState::unserialize(Checkpoint *cp, const std::string §ion)
92{
93
94 UNSERIALIZE_ENUM(_status);
95 // thread_num and cpu_id are deterministic from the config
96 UNSERIALIZE_SCALAR(funcExeInst);
97
98#if FULL_SYSTEM
99 Tick quiesceEndTick;
100 UNSERIALIZE_SCALAR(quiesceEndTick);
101 if (quiesceEndTick)
102 baseCpu->schedule(quiesceEvent, quiesceEndTick);
103 if (kernelStats)
104 kernelStats->unserialize(cp, section);
105#endif
106}
107
108void
109ThreadState::connectPhysPort()
110{
111 // @todo: For now this disregards any older port that may have
112 // already existed. Fix this memory leak once the bus port IDs
113 // for functional ports is resolved.
114 if (physPort)
115 physPort->removeConn();
116 else
117 physPort = new FunctionalPort(csprintf("%s-%d-funcport",
118 baseCpu->name(), _threadId));
119 connectToMemFunc(physPort);
120}
121
122void
123ThreadState::connectVirtPort(ThreadContext *tc)
124{
125 // @todo: For now this disregards any older port that may have
126 // already existed. Fix this memory leak once the bus port IDs
127 // for functional ports is resolved.
128 if (virtPort)
129 virtPort->removeConn();
130 else
131 virtPort = new VirtualPort(csprintf("%s-%d-vport",
132 baseCpu->name(), _threadId), tc);
133 connectToMemFunc(virtPort);
134}
135
136#if FULL_SYSTEM
137void
138ThreadState::connectMemPorts(ThreadContext *tc)
139{
140 connectPhysPort();
141 connectVirtPort(tc);
142}
143
144void
145ThreadState::profileClear()
146{
147 if (profile)
148 profile->clear();
149}
150
151void
152ThreadState::profileSample()
153{
154 if (profile)
155 profile->sample(profileNode, profilePC);
156}
157#endif
158
159TranslatingPort *
160ThreadState::getMemPort()
161{
162 if (port != NULL)
163 return port;
164
165 /* Use this port to for syscall emulation writes to memory. */
166 port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(),
| 63}
64
65void
66ThreadState::serialize(std::ostream &os)
67{
68 SERIALIZE_ENUM(_status);
69 // thread_num and cpu_id are deterministic from the config
70 SERIALIZE_SCALAR(funcExeInst);
71
72#if FULL_SYSTEM
73 Tick quiesceEndTick = 0;
74 if (quiesceEvent->scheduled())
75 quiesceEndTick = quiesceEvent->when();
76 SERIALIZE_SCALAR(quiesceEndTick);
77 if (kernelStats)
78 kernelStats->serialize(os);
79#endif
80}
81
82void
83ThreadState::unserialize(Checkpoint *cp, const std::string §ion)
84{
85
86 UNSERIALIZE_ENUM(_status);
87 // thread_num and cpu_id are deterministic from the config
88 UNSERIALIZE_SCALAR(funcExeInst);
89
90#if FULL_SYSTEM
91 Tick quiesceEndTick;
92 UNSERIALIZE_SCALAR(quiesceEndTick);
93 if (quiesceEndTick)
94 baseCpu->schedule(quiesceEvent, quiesceEndTick);
95 if (kernelStats)
96 kernelStats->unserialize(cp, section);
97#endif
98}
99
100void
101ThreadState::connectPhysPort()
102{
103 // @todo: For now this disregards any older port that may have
104 // already existed. Fix this memory leak once the bus port IDs
105 // for functional ports is resolved.
106 if (physPort)
107 physPort->removeConn();
108 else
109 physPort = new FunctionalPort(csprintf("%s-%d-funcport",
110 baseCpu->name(), _threadId));
111 connectToMemFunc(physPort);
112}
113
114void
115ThreadState::connectVirtPort(ThreadContext *tc)
116{
117 // @todo: For now this disregards any older port that may have
118 // already existed. Fix this memory leak once the bus port IDs
119 // for functional ports is resolved.
120 if (virtPort)
121 virtPort->removeConn();
122 else
123 virtPort = new VirtualPort(csprintf("%s-%d-vport",
124 baseCpu->name(), _threadId), tc);
125 connectToMemFunc(virtPort);
126}
127
128#if FULL_SYSTEM
129void
130ThreadState::connectMemPorts(ThreadContext *tc)
131{
132 connectPhysPort();
133 connectVirtPort(tc);
134}
135
136void
137ThreadState::profileClear()
138{
139 if (profile)
140 profile->clear();
141}
142
143void
144ThreadState::profileSample()
145{
146 if (profile)
147 profile->sample(profileNode, profilePC);
148}
149#endif
150
151TranslatingPort *
152ThreadState::getMemPort()
153{
154 if (port != NULL)
155 return port;
156
157 /* Use this port to for syscall emulation writes to memory. */
158 port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(),
|
167 _threadId),
168#if !FULL_SYSTEM
169 process,
170#endif
171 TranslatingPort::NextPage);
| 159 _threadId), process, TranslatingPort::NextPage);
|
172
173 connectToMemFunc(port);
174
175 return port;
176}
177
178void
179ThreadState::connectToMemFunc(Port *port)
180{
181 Port *dcache_port, *func_mem_port;
182
183 dcache_port = baseCpu->getPort("dcache_port");
184 assert(dcache_port != NULL);
185
186 MemObject *mem_object = dcache_port->getPeer()->getOwner();
187 assert(mem_object != NULL);
188
189 func_mem_port = mem_object->getPort("functional");
190 assert(func_mem_port != NULL);
191
192 func_mem_port->setPeer(port);
193 port->setPeer(func_mem_port);
194}
| 160
161 connectToMemFunc(port);
162
163 return port;
164}
165
166void
167ThreadState::connectToMemFunc(Port *port)
168{
169 Port *dcache_port, *func_mem_port;
170
171 dcache_port = baseCpu->getPort("dcache_port");
172 assert(dcache_port != NULL);
173
174 MemObject *mem_object = dcache_port->getPeer()->getOwner();
175 assert(mem_object != NULL);
176
177 func_mem_port = mem_object->getPort("functional");
178 assert(func_mem_port != NULL);
179
180 func_mem_port->setPeer(port);
181 port->setPeer(func_mem_port);
182}
|