1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "base/output.hh"
| 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "base/output.hh"
|
| 32#include "cpu/base.hh"
|
32#include "cpu/profile.hh" 33#include "cpu/thread_state.hh"
| 33#include "cpu/profile.hh" 34#include "cpu/thread_state.hh"
|
| 35#include "mem/port.hh" 36#include "mem/translating_port.hh"
|
34#include "sim/serialize.hh" 35 36#if FULL_SYSTEM 37#include "cpu/quiesce_event.hh" 38#include "kern/kernel_stats.hh" 39#endif 40 41#if FULL_SYSTEM
| 37#include "sim/serialize.hh" 38 39#if FULL_SYSTEM 40#include "cpu/quiesce_event.hh" 41#include "kern/kernel_stats.hh" 42#endif 43 44#if FULL_SYSTEM
|
42ThreadState::ThreadState(int _cpuId, int _tid) 43 : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
| 45ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid) 46 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
|
44 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
| 47 profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
|
| 48 physPort(NULL), virtPort(NULL),
|
45 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 46#else
| 49 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 50#else
|
47ThreadState::ThreadState(int _cpuId, int _tid, Process *_process, 48 short _asid, MemObject *mem) 49 : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 50 process(_process), asid(_asid),
| 51ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 52 short _asid) 53 : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 54 port(NULL), process(_process), asid(_asid),
|
51 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 52#endif 53{ 54 numInst = 0; 55 numLoad = 0; 56} 57 58void 59ThreadState::serialize(std::ostream &os) 60{ 61 SERIALIZE_ENUM(_status); 62 // thread_num and cpu_id are deterministic from the config 63 SERIALIZE_SCALAR(funcExeInst); 64 SERIALIZE_SCALAR(inst); 65 66#if FULL_SYSTEM 67 Tick quiesceEndTick = 0; 68 if (quiesceEvent->scheduled()) 69 quiesceEndTick = quiesceEvent->when(); 70 SERIALIZE_SCALAR(quiesceEndTick); 71 if (kernelStats) 72 kernelStats->serialize(os); 73#endif 74} 75 76void 77ThreadState::unserialize(Checkpoint *cp, const std::string §ion) 78{ 79 80 UNSERIALIZE_ENUM(_status); 81 // thread_num and cpu_id are deterministic from the config 82 UNSERIALIZE_SCALAR(funcExeInst); 83 UNSERIALIZE_SCALAR(inst); 84 85#if FULL_SYSTEM 86 Tick quiesceEndTick; 87 UNSERIALIZE_SCALAR(quiesceEndTick); 88 if (quiesceEndTick) 89 quiesceEvent->schedule(quiesceEndTick); 90 if (kernelStats) 91 kernelStats->unserialize(cp, section); 92#endif 93} 94 95#if FULL_SYSTEM 96 97void 98ThreadState::profileClear() 99{ 100 if (profile) 101 profile->clear(); 102} 103 104void 105ThreadState::profileSample() 106{ 107 if (profile) 108 profile->sample(profileNode, profilePC); 109} 110
| 55 microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 56#endif 57{ 58 numInst = 0; 59 numLoad = 0; 60} 61 62void 63ThreadState::serialize(std::ostream &os) 64{ 65 SERIALIZE_ENUM(_status); 66 // thread_num and cpu_id are deterministic from the config 67 SERIALIZE_SCALAR(funcExeInst); 68 SERIALIZE_SCALAR(inst); 69 70#if FULL_SYSTEM 71 Tick quiesceEndTick = 0; 72 if (quiesceEvent->scheduled()) 73 quiesceEndTick = quiesceEvent->when(); 74 SERIALIZE_SCALAR(quiesceEndTick); 75 if (kernelStats) 76 kernelStats->serialize(os); 77#endif 78} 79 80void 81ThreadState::unserialize(Checkpoint *cp, const std::string §ion) 82{ 83 84 UNSERIALIZE_ENUM(_status); 85 // thread_num and cpu_id are deterministic from the config 86 UNSERIALIZE_SCALAR(funcExeInst); 87 UNSERIALIZE_SCALAR(inst); 88 89#if FULL_SYSTEM 90 Tick quiesceEndTick; 91 UNSERIALIZE_SCALAR(quiesceEndTick); 92 if (quiesceEndTick) 93 quiesceEvent->schedule(quiesceEndTick); 94 if (kernelStats) 95 kernelStats->unserialize(cp, section); 96#endif 97} 98 99#if FULL_SYSTEM 100 101void 102ThreadState::profileClear() 103{ 104 if (profile) 105 profile->clear(); 106} 107 108void 109ThreadState::profileSample() 110{ 111 if (profile) 112 profile->sample(profileNode, profilePC); 113} 114
|
| 115#else 116TranslatingPort * 117ThreadState::getMemPort() 118{ 119 if (port != NULL) 120 return port; 121 122 /* Use this port to for syscall emulation writes to memory. */ 123 Port *dcache_port, *func_mem_port; 124 port = new TranslatingPort(csprintf("%s-%d-funcport", 125 baseCpu->name(), tid), 126 process->pTable, false); 127 128 dcache_port = baseCpu->getPort("dcache_port"); 129 assert(dcache_port != NULL); 130 131 MemObject *mem_object = dcache_port->getPeer()->getOwner(); 132 assert(mem_object != NULL); 133 134 func_mem_port = mem_object->getPort("functional"); 135 assert(func_mem_port != NULL); 136 137 func_mem_port->setPeer(port); 138 port->setPeer(func_mem_port); 139 140 return port; 141}
|
111#endif
| 142#endif
|