thread_context.hh (9441:1133617844c8) thread_context.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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91 */
92class ThreadContext
93{
94 protected:
95 typedef TheISA::MachInst MachInst;
96 typedef TheISA::IntReg IntReg;
97 typedef TheISA::FloatReg FloatReg;
98 typedef TheISA::FloatRegBits FloatRegBits;
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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92 */
93class ThreadContext
94{
95 protected:
96 typedef TheISA::MachInst MachInst;
97 typedef TheISA::IntReg IntReg;
98 typedef TheISA::FloatReg FloatReg;
99 typedef TheISA::FloatRegBits FloatRegBits;
100 typedef TheISA::CCReg CCReg;
99 typedef TheISA::MiscReg MiscReg;
100 public:
101
102 enum Status
103 {
104 /// Running. Instructions should be executed only when
105 /// the context is in this state.
106 Active,

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195 // New accessors for new decoder.
196 //
197 virtual uint64_t readIntReg(int reg_idx) = 0;
198
199 virtual FloatReg readFloatReg(int reg_idx) = 0;
200
201 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
202
101 typedef TheISA::MiscReg MiscReg;
102 public:
103
104 enum Status
105 {
106 /// Running. Instructions should be executed only when
107 /// the context is in this state.
108 Active,

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197 // New accessors for new decoder.
198 //
199 virtual uint64_t readIntReg(int reg_idx) = 0;
200
201 virtual FloatReg readFloatReg(int reg_idx) = 0;
202
203 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
204
205 virtual CCReg readCCReg(int reg_idx) = 0;
206
203 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
204
205 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
206
207 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
208
207 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
208
209 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
210
211 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
212
213 virtual void setCCReg(int reg_idx, CCReg val) = 0;
214
209 virtual TheISA::PCState pcState() = 0;
210
211 virtual void pcState(const TheISA::PCState &val) = 0;
212
213 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
214
215 virtual Addr instAddr() = 0;
216

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223 virtual MiscReg readMiscReg(int misc_reg) = 0;
224
225 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
226
227 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
228
229 virtual int flattenIntIndex(int reg) = 0;
230 virtual int flattenFloatIndex(int reg) = 0;
215 virtual TheISA::PCState pcState() = 0;
216
217 virtual void pcState(const TheISA::PCState &val) = 0;
218
219 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
220
221 virtual Addr instAddr() = 0;
222

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229 virtual MiscReg readMiscReg(int misc_reg) = 0;
230
231 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
232
233 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
234
235 virtual int flattenIntIndex(int reg) = 0;
236 virtual int flattenFloatIndex(int reg) = 0;
237 virtual int flattenCCIndex(int reg) = 0;
231
232 virtual uint64_t
233 readRegOtherThread(int misc_reg, ThreadID tid)
234 {
235 return 0;
236 }
237
238 virtual void

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278 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
279
280 virtual FloatReg readFloatRegFlat(int idx) = 0;
281 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
282
283 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
284 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
285
238
239 virtual uint64_t
240 readRegOtherThread(int misc_reg, ThreadID tid)
241 {
242 return 0;
243 }
244
245 virtual void

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285 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
286
287 virtual FloatReg readFloatRegFlat(int idx) = 0;
288 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
289
290 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
291 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
292
293 virtual CCReg readCCRegFlat(int idx) = 0;
294 virtual void setCCRegFlat(int idx, CCReg val) = 0;
286 /** @} */
287
288};
289
290/**
291 * ProxyThreadContext class that provides a way to implement a
292 * ThreadContext without having to derive from it. ThreadContext is an
293 * abstract class, so anything that derives from it and uses its

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386 { return actualTC->readIntReg(reg_idx); }
387
388 FloatReg readFloatReg(int reg_idx)
389 { return actualTC->readFloatReg(reg_idx); }
390
391 FloatRegBits readFloatRegBits(int reg_idx)
392 { return actualTC->readFloatRegBits(reg_idx); }
393
295 /** @} */
296
297};
298
299/**
300 * ProxyThreadContext class that provides a way to implement a
301 * ThreadContext without having to derive from it. ThreadContext is an
302 * abstract class, so anything that derives from it and uses its

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395 { return actualTC->readIntReg(reg_idx); }
396
397 FloatReg readFloatReg(int reg_idx)
398 { return actualTC->readFloatReg(reg_idx); }
399
400 FloatRegBits readFloatRegBits(int reg_idx)
401 { return actualTC->readFloatRegBits(reg_idx); }
402
403 CCReg readCCReg(int reg_idx)
404 { return actualTC->readCCReg(reg_idx); }
405
394 void setIntReg(int reg_idx, uint64_t val)
395 { actualTC->setIntReg(reg_idx, val); }
396
397 void setFloatReg(int reg_idx, FloatReg val)
398 { actualTC->setFloatReg(reg_idx, val); }
399
400 void setFloatRegBits(int reg_idx, FloatRegBits val)
401 { actualTC->setFloatRegBits(reg_idx, val); }
402
406 void setIntReg(int reg_idx, uint64_t val)
407 { actualTC->setIntReg(reg_idx, val); }
408
409 void setFloatReg(int reg_idx, FloatReg val)
410 { actualTC->setFloatReg(reg_idx, val); }
411
412 void setFloatRegBits(int reg_idx, FloatRegBits val)
413 { actualTC->setFloatRegBits(reg_idx, val); }
414
415 void setCCReg(int reg_idx, CCReg val)
416 { actualTC->setCCReg(reg_idx, val); }
417
403 TheISA::PCState pcState() { return actualTC->pcState(); }
404
405 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
406
407 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
408
409 Addr instAddr() { return actualTC->instAddr(); }
410 Addr nextInstAddr() { return actualTC->nextInstAddr(); }

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428 { return actualTC->setMiscReg(misc_reg, val); }
429
430 int flattenIntIndex(int reg)
431 { return actualTC->flattenIntIndex(reg); }
432
433 int flattenFloatIndex(int reg)
434 { return actualTC->flattenFloatIndex(reg); }
435
418 TheISA::PCState pcState() { return actualTC->pcState(); }
419
420 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
421
422 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
423
424 Addr instAddr() { return actualTC->instAddr(); }
425 Addr nextInstAddr() { return actualTC->nextInstAddr(); }

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443 { return actualTC->setMiscReg(misc_reg, val); }
444
445 int flattenIntIndex(int reg)
446 { return actualTC->flattenIntIndex(reg); }
447
448 int flattenFloatIndex(int reg)
449 { return actualTC->flattenFloatIndex(reg); }
450
451 int flattenCCIndex(int reg)
452 { return actualTC->flattenCCIndex(reg); }
453
436 unsigned readStCondFailures()
437 { return actualTC->readStCondFailures(); }
438
439 void setStCondFailures(unsigned sc_failures)
440 { actualTC->setStCondFailures(sc_failures); }
441
442 // @todo: Fix this!
443 bool misspeculating() { return actualTC->misspeculating(); }

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459 void setFloatRegFlat(int idx, FloatReg val)
460 { actualTC->setFloatRegFlat(idx, val); }
461
462 FloatRegBits readFloatRegBitsFlat(int idx)
463 { return actualTC->readFloatRegBitsFlat(idx); }
464
465 void setFloatRegBitsFlat(int idx, FloatRegBits val)
466 { actualTC->setFloatRegBitsFlat(idx, val); }
454 unsigned readStCondFailures()
455 { return actualTC->readStCondFailures(); }
456
457 void setStCondFailures(unsigned sc_failures)
458 { actualTC->setStCondFailures(sc_failures); }
459
460 // @todo: Fix this!
461 bool misspeculating() { return actualTC->misspeculating(); }

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477 void setFloatRegFlat(int idx, FloatReg val)
478 { actualTC->setFloatRegFlat(idx, val); }
479
480 FloatRegBits readFloatRegBitsFlat(int idx)
481 { return actualTC->readFloatRegBitsFlat(idx); }
482
483 void setFloatRegBitsFlat(int idx, FloatRegBits val)
484 { actualTC->setFloatRegBitsFlat(idx, val); }
485
486 CCReg readCCRegFlat(int idx)
487 { return actualTC->readCCRegFlat(idx); }
488
489 void setCCRegFlat(int idx, CCReg val)
490 { actualTC->setCCRegFlat(idx, val); }
467};
468
469/** @{ */
470/**
471 * Thread context serialization helpers
472 *
473 * These helper functions provide a way to the data in a
474 * ThreadContext. They are provided as separate helper function since

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492
493/** @{ */
494/**
495 * Thread context serialization helpers
496 *
497 * These helper functions provide a way to the data in a
498 * ThreadContext. They are provided as separate helper function since

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