thread_context.hh (8852:c744483edfcf) | thread_context.hh (8887:20ea02da9c53) |
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1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 36 unchanged lines hidden (view full) --- 45 46#include <iostream> 47#include <string> 48 49#include "arch/registers.hh" 50#include "arch/types.hh" 51#include "base/types.hh" 52#include "config/the_isa.hh" | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 36 unchanged lines hidden (view full) --- 45 46#include <iostream> 47#include <string> 48 49#include "arch/registers.hh" 50#include "arch/types.hh" 51#include "base/types.hh" 52#include "config/the_isa.hh" |
53#include "config/use_checker.hh" | |
54 55// @todo: Figure out a more architecture independent way to obtain the ITB and 56// DTB pointers. 57namespace TheISA 58{ 59 class TLB; 60} 61class BaseCPU; | 53 54// @todo: Figure out a more architecture independent way to obtain the ITB and 55// DTB pointers. 56namespace TheISA 57{ 58 class TLB; 59} 60class BaseCPU; |
61class CheckerCPU; |
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62class Checkpoint; 63class Decoder; 64class EndQuiesceEvent; 65class SETranslatingPortProxy; 66class FSTranslatingPortProxy; 67class PortProxy; 68class Process; 69class System; --- 58 unchanged lines hidden (view full) --- 128 virtual int contextId() = 0; 129 130 virtual void setContextId(int id) = 0; 131 132 virtual TheISA::TLB *getITBPtr() = 0; 133 134 virtual TheISA::TLB *getDTBPtr() = 0; 135 | 62class Checkpoint; 63class Decoder; 64class EndQuiesceEvent; 65class SETranslatingPortProxy; 66class FSTranslatingPortProxy; 67class PortProxy; 68class Process; 69class System; --- 58 unchanged lines hidden (view full) --- 128 virtual int contextId() = 0; 129 130 virtual void setContextId(int id) = 0; 131 132 virtual TheISA::TLB *getITBPtr() = 0; 133 134 virtual TheISA::TLB *getDTBPtr() = 0; 135 |
136#if USE_CHECKER 137 virtual BaseCPU *getCheckerCpuPtr() = 0; 138#endif | 136 virtual CheckerCPU *getCheckerCpuPtr() = 0; |
139 140 virtual Decoder *getDecoderPtr() = 0; 141 142 virtual System *getSystemPtr() = 0; 143 144 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 145 146 virtual PortProxy &getPhysProxy() = 0; --- 63 unchanged lines hidden (view full) --- 210 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 211 212 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 213 214 virtual TheISA::PCState pcState() = 0; 215 216 virtual void pcState(const TheISA::PCState &val) = 0; 217 | 137 138 virtual Decoder *getDecoderPtr() = 0; 139 140 virtual System *getSystemPtr() = 0; 141 142 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 143 144 virtual PortProxy &getPhysProxy() = 0; --- 63 unchanged lines hidden (view full) --- 208 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 209 210 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 211 212 virtual TheISA::PCState pcState() = 0; 213 214 virtual void pcState(const TheISA::PCState &val) = 0; 215 |
218#if USE_CHECKER | |
219 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; | 216 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; |
220#endif | |
221 222 virtual Addr instAddr() = 0; 223 224 virtual Addr nextInstAddr() = 0; 225 226 virtual MicroPC microPC() = 0; 227 228 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; --- 74 unchanged lines hidden (view full) --- 303 int contextId() { return actualTC->contextId(); } 304 305 void setContextId(int id) { actualTC->setContextId(id); } 306 307 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 308 309 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 310 | 217 218 virtual Addr instAddr() = 0; 219 220 virtual Addr nextInstAddr() = 0; 221 222 virtual MicroPC microPC() = 0; 223 224 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; --- 74 unchanged lines hidden (view full) --- 299 int contextId() { return actualTC->contextId(); } 300 301 void setContextId(int id) { actualTC->setContextId(id); } 302 303 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 304 305 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 306 |
311#if USE_CHECKER 312 BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 313#endif | 307 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } |
314 315 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 316 317 System *getSystemPtr() { return actualTC->getSystemPtr(); } 318 319 TheISA::Kernel::Statistics *getKernelStats() 320 { return actualTC->getKernelStats(); } 321 --- 65 unchanged lines hidden (view full) --- 387 388 void setFloatRegBits(int reg_idx, FloatRegBits val) 389 { actualTC->setFloatRegBits(reg_idx, val); } 390 391 TheISA::PCState pcState() { return actualTC->pcState(); } 392 393 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 394 | 308 309 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 310 311 System *getSystemPtr() { return actualTC->getSystemPtr(); } 312 313 TheISA::Kernel::Statistics *getKernelStats() 314 { return actualTC->getKernelStats(); } 315 --- 65 unchanged lines hidden (view full) --- 381 382 void setFloatRegBits(int reg_idx, FloatRegBits val) 383 { actualTC->setFloatRegBits(reg_idx, val); } 384 385 TheISA::PCState pcState() { return actualTC->pcState(); } 386 387 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 388 |
395#if USE_CHECKER | |
396 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } | 389 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } |
397#endif | |
398 399 Addr instAddr() { return actualTC->instAddr(); } 400 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 401 MicroPC microPC() { return actualTC->microPC(); } 402 403 bool readPredicate() { return actualTC->readPredicate(); } 404 405 void setPredicate(bool val) --- 36 unchanged lines hidden --- | 390 391 Addr instAddr() { return actualTC->instAddr(); } 392 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 393 MicroPC microPC() { return actualTC->microPC(); } 394 395 bool readPredicate() { return actualTC->readPredicate(); } 396 397 void setPredicate(bool val) --- 36 unchanged lines hidden --- |