thread_context.hh (8777:dd43f1c9fa0a) thread_context.hh (8799:dac1e33e07b0)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44namespace TheISA
45{
46 class TLB;
47}
48class BaseCPU;
49class Checkpoint;
50class Decoder;
51class EndQuiesceEvent;
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44namespace TheISA
45{
46 class TLB;
47}
48class BaseCPU;
49class Checkpoint;
50class Decoder;
51class EndQuiesceEvent;
52class TranslatingPort;
53class FunctionalPort;
54class VirtualPort;
52class SETranslatingPortProxy;
53class FSTranslatingPortProxy;
54class PortProxy;
55class Process;
56class System;
57namespace TheISA {
58 namespace Kernel {
59 class Statistics;
60 };
61};
62

--- 58 unchanged lines hidden (view full) ---

121 virtual TheISA::TLB *getDTBPtr() = 0;
122
123 virtual Decoder *getDecoderPtr() = 0;
124
125 virtual System *getSystemPtr() = 0;
126
127 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
128
55class Process;
56class System;
57namespace TheISA {
58 namespace Kernel {
59 class Statistics;
60 };
61};
62

--- 58 unchanged lines hidden (view full) ---

121 virtual TheISA::TLB *getDTBPtr() = 0;
122
123 virtual Decoder *getDecoderPtr() = 0;
124
125 virtual System *getSystemPtr() = 0;
126
127 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
128
129 virtual void connectMemPorts(ThreadContext *tc) = 0;
129 virtual PortProxy* getPhysProxy() = 0;
130
130
131 virtual Process *getProcessPtr() = 0;
131 virtual FSTranslatingPortProxy* getVirtProxy() = 0;
132
132
133 virtual TranslatingPort *getMemPort() = 0;
133 /**
134 * Initialise the physical and virtual port proxies and tie them to
135 * the data port of the CPU.
136 *
137 * tc ThreadContext for the virtual-to-physical translation
138 */
139 virtual void initMemProxies(ThreadContext *tc) = 0;
134
140
135 virtual VirtualPort *getVirtPort() = 0;
141 virtual SETranslatingPortProxy *getMemProxy() = 0;
136
142
137 virtual FunctionalPort *getPhysPort() = 0;
143 virtual Process *getProcessPtr() = 0;
138
139 virtual Status status() const = 0;
140
141 virtual void setStatus(Status new_status) = 0;
142
143 /// Set the status to Active. Optional delay indicates number of
144 /// cycles to wait before beginning execution.
145 virtual void activate(int delay = 1) = 0;

--- 137 unchanged lines hidden (view full) ---

283
284 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
285
286 System *getSystemPtr() { return actualTC->getSystemPtr(); }
287
288 TheISA::Kernel::Statistics *getKernelStats()
289 { return actualTC->getKernelStats(); }
290
144
145 virtual Status status() const = 0;
146
147 virtual void setStatus(Status new_status) = 0;
148
149 /// Set the status to Active. Optional delay indicates number of
150 /// cycles to wait before beginning execution.
151 virtual void activate(int delay = 1) = 0;

--- 137 unchanged lines hidden (view full) ---

289
290 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
291
292 System *getSystemPtr() { return actualTC->getSystemPtr(); }
293
294 TheISA::Kernel::Statistics *getKernelStats()
295 { return actualTC->getKernelStats(); }
296
291 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
297 PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); }
292
298
293 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
299 FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); }
294
300
295 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
301 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
296
302
297 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
303 SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
298
304
299 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
305 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
300
301 Status status() const { return actualTC->status(); }
302
303 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
304
305 /// Set the status to Active. Optional delay indicates number of
306 /// cycles to wait before beginning execution.
307 void activate(int delay = 1) { actualTC->activate(delay); }

--- 99 unchanged lines hidden --- 		306
307 Status status() const { return actualTC->status(); }
308
309 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
310
311 /// Set the status to Active. Optional delay indicates number of
312 /// cycles to wait before beginning execution.
313 void activate(int delay = 1) { actualTC->activate(delay); }

--- 99 unchanged lines hidden ---