thread_context.hh (5217:bb810bb8ca2d) thread_context.hh (5222:bb733a878f85)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
234
235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
236
237 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
238
239 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
240
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 224 unchanged lines hidden (view full) ---

233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
234
235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
236
237 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
238
239 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
240
241 virtual void setShadowSet(int css) = 0;
242
241 // Also not necessarily the best location for these two. Hopefully will go
242 // away once we decide upon where st cond failures goes.
243 virtual unsigned readStCondFailures() = 0;
244
245 virtual void setStCondFailures(unsigned sc_failures) = 0;
246
247 // Only really makes sense for old CPU model. Still could be useful though.
248 virtual bool misspeculating() = 0;

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402 { actualTC->setFloatReg(reg_idx, val); }
403
404 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
405 { actualTC->setFloatRegBits(reg_idx, val, width); }
406
407 void setFloatRegBits(int reg_idx, FloatRegBits val)
408 { actualTC->setFloatRegBits(reg_idx, val); }
409
243 // Also not necessarily the best location for these two. Hopefully will go
244 // away once we decide upon where st cond failures goes.
245 virtual unsigned readStCondFailures() = 0;
246
247 virtual void setStCondFailures(unsigned sc_failures) = 0;
248
249 // Only really makes sense for old CPU model. Still could be useful though.
250 virtual bool misspeculating() = 0;

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404 { actualTC->setFloatReg(reg_idx, val); }
405
406 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
407 { actualTC->setFloatRegBits(reg_idx, val, width); }
408
409 void setFloatRegBits(int reg_idx, FloatRegBits val)
410 { actualTC->setFloatRegBits(reg_idx, val); }
411
412 void setShadowSet(int css){
413 return actualTC->setShadowSet(css);
414 }
415
410 uint64_t readPC() { return actualTC->readPC(); }
411
412 void setPC(uint64_t val) { actualTC->setPC(val); }
413
414 uint64_t readNextPC() { return actualTC->readNextPC(); }
415
416 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
417

--- 49 unchanged lines hidden --- 		416 uint64_t readPC() { return actualTC->readPC(); }
417
418 void setPC(uint64_t val) { actualTC->setPC(val); }
419
420 uint64_t readNextPC() { return actualTC->readNextPC(); }
421
422 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
423

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