thread_context.hh (4111:65fffcb4fae9) thread_context.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 212 unchanged lines hidden (view full) ---

221 virtual uint64_t readNextPC() = 0;
222
223 virtual void setNextPC(uint64_t val) = 0;
224
225 virtual uint64_t readNextNPC() = 0;
226
227 virtual void setNextNPC(uint64_t val) = 0;
228
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 212 unchanged lines hidden (view full) ---

221 virtual uint64_t readNextPC() = 0;
222
223 virtual void setNextPC(uint64_t val) = 0;
224
225 virtual uint64_t readNextNPC() = 0;
226
227 virtual void setNextNPC(uint64_t val) = 0;
228
229 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
230
229 virtual MiscReg readMiscReg(int misc_reg) = 0;
230
231 virtual MiscReg readMiscReg(int misc_reg) = 0;
232
231 virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
232
233 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
234
234
235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
236
235 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
236
237 // Also not necessarily the best location for these two. Hopefully will go
238 // away once we decide upon where st cond failures goes.
239 virtual unsigned readStCondFailures() = 0;
240
241 virtual void setStCondFailures(unsigned sc_failures) = 0;
242
243 // Only really makes sense for old CPU model. Still could be useful though.
244 virtual bool misspeculating() = 0;

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407 uint64_t readNextPC() { return actualTC->readNextPC(); }
408
409 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
410
411 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
412
413 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
414
237 // Also not necessarily the best location for these two. Hopefully will go
238 // away once we decide upon where st cond failures goes.
239 virtual unsigned readStCondFailures() = 0;
240
241 virtual void setStCondFailures(unsigned sc_failures) = 0;
242
243 // Only really makes sense for old CPU model. Still could be useful though.
244 virtual bool misspeculating() = 0;

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407 uint64_t readNextPC() { return actualTC->readNextPC(); }
408
409 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
410
411 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
412
413 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
414
415 MiscReg readMiscRegNoEffect(int misc_reg)
416 { return actualTC->readMiscRegNoEffect(misc_reg); }
417
415 MiscReg readMiscReg(int misc_reg)
416 { return actualTC->readMiscReg(misc_reg); }
417
418 MiscReg readMiscReg(int misc_reg)
419 { return actualTC->readMiscReg(misc_reg); }
420
418 MiscReg readMiscRegWithEffect(int misc_reg)
419 { return actualTC->readMiscRegWithEffect(misc_reg); }
421 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
422 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
420
421 void setMiscReg(int misc_reg, const MiscReg &val)
422 { return actualTC->setMiscReg(misc_reg, val); }
423
423
424 void setMiscReg(int misc_reg, const MiscReg &val)
425 { return actualTC->setMiscReg(misc_reg, val); }
426
424 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
425 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
426
427 unsigned readStCondFailures()
428 { return actualTC->readStCondFailures(); }
429
430 void setStCondFailures(unsigned sc_failures)
431 { actualTC->setStCondFailures(sc_failures); }
432
433 // @todo: Fix this!
434 bool misspeculating() { return actualTC->misspeculating(); }

--- 25 unchanged lines hidden --- 		427 unsigned readStCondFailures()
428 { return actualTC->readStCondFailures(); }
429
430 void setStCondFailures(unsigned sc_failures)
431 { actualTC->setStCondFailures(sc_failures); }
432
433 // @todo: Fix this!
434 bool misspeculating() { return actualTC->misspeculating(); }

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