thread_context.hh (3453:c3ce58882751) thread_context.hh (3468:cf23ad1ceef2)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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219 virtual void setNextPC(uint64_t val) = 0;
220
221 virtual uint64_t readNextNPC() = 0;
222
223 virtual void setNextNPC(uint64_t val) = 0;
224
225 virtual MiscReg readMiscReg(int misc_reg) = 0;
226
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 210 unchanged lines hidden (view full) ---

219 virtual void setNextPC(uint64_t val) = 0;
220
221 virtual uint64_t readNextNPC() = 0;
222
223 virtual void setNextNPC(uint64_t val) = 0;
224
225 virtual MiscReg readMiscReg(int misc_reg) = 0;
226
227 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
227 virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
228
228
229 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
229 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
230
230
231 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
231 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
232
233 // Also not necessarily the best location for these two. Hopefully will go
234 // away once we decide upon where st cond failures goes.
235 virtual unsigned readStCondFailures() = 0;
236
237 virtual void setStCondFailures(unsigned sc_failures) = 0;
238
239#if FULL_SYSTEM

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405
406 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
407
408 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
409
410 MiscReg readMiscReg(int misc_reg)
411 { return actualTC->readMiscReg(misc_reg); }
412
232
233 // Also not necessarily the best location for these two. Hopefully will go
234 // away once we decide upon where st cond failures goes.
235 virtual unsigned readStCondFailures() = 0;
236
237 virtual void setStCondFailures(unsigned sc_failures) = 0;
238
239#if FULL_SYSTEM

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405
406 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
407
408 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
409
410 MiscReg readMiscReg(int misc_reg)
411 { return actualTC->readMiscReg(misc_reg); }
412
413 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
414 { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
413 MiscReg readMiscRegWithEffect(int misc_reg)
414 { return actualTC->readMiscRegWithEffect(misc_reg); }
415
415
416 Fault setMiscReg(int misc_reg, const MiscReg &val)
416 void setMiscReg(int misc_reg, const MiscReg &val)
417 { return actualTC->setMiscReg(misc_reg, val); }
418
417 { return actualTC->setMiscReg(misc_reg, val); }
418
419 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
419 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
420 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
421
422 unsigned readStCondFailures()
423 { return actualTC->readStCondFailures(); }
424
425 void setStCondFailures(unsigned sc_failures)
426 { actualTC->setStCondFailures(sc_failures); }
427#if FULL_SYSTEM

--- 27 unchanged lines hidden --- 		420 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
421
422 unsigned readStCondFailures()
423 { return actualTC->readStCondFailures(); }
424
425 void setStCondFailures(unsigned sc_failures)
426 { actualTC->setStCondFailures(sc_failures); }
427#if FULL_SYSTEM

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