thread_context.hh (13693:85fa3a41014b) thread_context.hh (13865:cca49fc49c57)
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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76 }
77}
78
79/**
80 * ThreadContext is the external interface to all thread state for
81 * anything outside of the CPU. It provides all accessor methods to
82 * state that might be needed by external objects, ranging from
83 * register values to things such as kernel stats. It is an abstract
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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76 }
77}
78
79/**
80 * ThreadContext is the external interface to all thread state for
81 * anything outside of the CPU. It provides all accessor methods to
82 * state that might be needed by external objects, ranging from
83 * register values to things such as kernel stats. It is an abstract
84 * base class; the CPU can create its own ThreadContext by either
85 * deriving from it, or using the templated ProxyThreadContext.
84 * base class; the CPU can create its own ThreadContext by
85 * deriving from it.
86 *
87 * The ThreadContext is slightly different than the ExecContext. The
88 * ThreadContext provides access to an individual thread's state; an
89 * ExecContext provides ISA access to the CPU (meaning it is
90 * implicitly multithreaded on SMT systems). Additionally the
91 * ThreadState is an abstract class that exactly defines the
92 * interface; the ExecContext is a more implicit interface that must
93 * be implemented so that the ISA can access whatever state it needs.

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129 virtual int cpuId() const = 0;
130
131 virtual uint32_t socketId() const = 0;
132
133 virtual int threadId() const = 0;
134
135 virtual void setThreadId(int id) = 0;
136
86 *
87 * The ThreadContext is slightly different than the ExecContext. The
88 * ThreadContext provides access to an individual thread's state; an
89 * ExecContext provides ISA access to the CPU (meaning it is
90 * implicitly multithreaded on SMT systems). Additionally the
91 * ThreadState is an abstract class that exactly defines the
92 * interface; the ExecContext is a more implicit interface that must
93 * be implemented so that the ISA can access whatever state it needs.

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129 virtual int cpuId() const = 0;
130
131 virtual uint32_t socketId() const = 0;
132
133 virtual int threadId() const = 0;
134
135 virtual void setThreadId(int id) = 0;
136
137 virtual int contextId() const = 0;
137 virtual ContextID contextId() const = 0;
138
138
139 virtual void setContextId(int id) = 0;
139 virtual void setContextId(ContextID id) = 0;
140
141 virtual BaseTLB *getITBPtr() = 0;
142
143 virtual BaseTLB *getDTBPtr() = 0;
144
145 virtual CheckerCPU *getCheckerCpuPtr() = 0;
146
147 virtual TheISA::ISA *getIsaPtr() = 0;

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207
208 virtual void copyArchRegs(ThreadContext *tc) = 0;
209
210 virtual void clearArchRegs() = 0;
211
212 //
213 // New accessors for new decoder.
214 //
140
141 virtual BaseTLB *getITBPtr() = 0;
142
143 virtual BaseTLB *getDTBPtr() = 0;
144
145 virtual CheckerCPU *getCheckerCpuPtr() = 0;
146
147 virtual TheISA::ISA *getIsaPtr() = 0;

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207
208 virtual void copyArchRegs(ThreadContext *tc) = 0;
209
210 virtual void clearArchRegs() = 0;
211
212 //
213 // New accessors for new decoder.
214 //
215 virtual RegVal readIntReg(int reg_idx) = 0;
215 virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
216
216
217 virtual RegVal readFloatReg(int reg_idx) = 0;
217 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
218
219 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
220 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
221
222 /** Vector Register Lane Interfaces. */
223 /** @{ */
224 /** Reads source vector 8bit operand. */
225 virtual ConstVecLane8

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249 /** @} */
250
251 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
252
253 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
254 const = 0;
255 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
256
218
219 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
220 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
221
222 /** Vector Register Lane Interfaces. */
223 /** @{ */
224 /** Reads source vector 8bit operand. */
225 virtual ConstVecLane8

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249 /** @} */
250
251 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
252
253 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
254 const = 0;
255 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
256
257 virtual RegVal readCCReg(int reg_idx) = 0;
257 virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
258
258
259 virtual void setIntReg(int reg_idx, RegVal val) = 0;
259 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
260
260
261 virtual void setFloatReg(int reg_idx, RegVal val) = 0;
261 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
262
263 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
264
265 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
266
267 virtual void setVecPredReg(const RegId& reg,
268 const VecPredRegContainer& val) = 0;
269
262
263 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
264
265 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
266
267 virtual void setVecPredReg(const RegId& reg,
268 const VecPredRegContainer& val) = 0;
269
270 virtual void setCCReg(int reg_idx, RegVal val) = 0;
270 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
271
271
272 virtual TheISA::PCState pcState() = 0;
272 virtual TheISA::PCState pcState() const = 0;
273
274 virtual void pcState(const TheISA::PCState &val) = 0;
275
276 void
277 setNPC(Addr val)
278 {
279 TheISA::PCState pc_state = pcState();
280 pc_state.setNPC(val);
281 pcState(pc_state);
282 }
283
284 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
285
273
274 virtual void pcState(const TheISA::PCState &val) = 0;
275
276 void
277 setNPC(Addr val)
278 {
279 TheISA::PCState pc_state = pcState();
280 pc_state.setNPC(val);
281 pcState(pc_state);
282 }
283
284 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
285
286 virtual Addr instAddr() = 0;
286 virtual Addr instAddr() const = 0;
287
287
288 virtual Addr nextInstAddr() = 0;
288 virtual Addr nextInstAddr() const = 0;
289
289
290 virtual MicroPC microPC() = 0;
290 virtual MicroPC microPC() const = 0;
291
291
292 virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0;
292 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
293
293
294 virtual RegVal readMiscReg(int misc_reg) = 0;
294 virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
295
295
296 virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
296 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
297
297
298 virtual void setMiscReg(int misc_reg, RegVal val) = 0;
298 virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
299
300 virtual RegId flattenRegId(const RegId& regId) const = 0;
301
302 virtual RegVal
303 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
304 {
305 return 0;
306 }
307
308 virtual void
309 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
310 {
311 }
312
313 // Also not necessarily the best location for these two. Hopefully will go
314 // away once we decide upon where st cond failures goes.
299
300 virtual RegId flattenRegId(const RegId& regId) const = 0;
301
302 virtual RegVal
303 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
304 {
305 return 0;
306 }
307
308 virtual void
309 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
310 {
311 }
312
313 // Also not necessarily the best location for these two. Hopefully will go
314 // away once we decide upon where st cond failures goes.
315 virtual unsigned readStCondFailures() = 0;
315 virtual unsigned readStCondFailures() const = 0;
316
317 virtual void setStCondFailures(unsigned sc_failures) = 0;
318
319 // Same with st cond failures.
316
317 virtual void setStCondFailures(unsigned sc_failures) = 0;
318
319 // Same with st cond failures.
320 virtual Counter readFuncExeInst() = 0;
320 virtual Counter readFuncExeInst() const = 0;
321
322 virtual void syscall(int64_t callnum, Fault *fault) = 0;
323
324 // This function exits the thread context in the CPU and returns
325 // 1 if the CPU has no more active threads (meaning it's OK to exit);
326 // Used in syscall-emulation mode when a thread calls the exit syscall.
327 virtual int exit() { return 1; };
328

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336 * Some architectures have different registers visible in
337 * different modes. Such architectures "flatten" a register (see
338 * flattenRegId()) to map it into the
339 * gem5 register file. This interface provides a flat interface to
340 * the underlying register file, which allows for example
341 * serialization code to access all registers.
342 */
343
321
322 virtual void syscall(int64_t callnum, Fault *fault) = 0;
323
324 // This function exits the thread context in the CPU and returns
325 // 1 if the CPU has no more active threads (meaning it's OK to exit);
326 // Used in syscall-emulation mode when a thread calls the exit syscall.
327 virtual int exit() { return 1; };
328

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336 * Some architectures have different registers visible in
337 * different modes. Such architectures "flatten" a register (see
338 * flattenRegId()) to map it into the
339 * gem5 register file. This interface provides a flat interface to
340 * the underlying register file, which allows for example
341 * serialization code to access all registers.
342 */
343
344 virtual RegVal readIntRegFlat(int idx) = 0;
345 virtual void setIntRegFlat(int idx, RegVal val) = 0;
344 virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
345 virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
346
346
347 virtual RegVal readFloatRegFlat(int idx) = 0;
348 virtual void setFloatRegFlat(int idx, RegVal val) = 0;
347 virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
348 virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
349
349
350 virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
351 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
352 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
350 virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
351 virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
352 virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
353
353
354 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
354 virtual const VecElem& readVecElemFlat(RegIndex idx,
355 const ElemIndex& elemIdx) const = 0;
355 const ElemIndex& elemIdx) const = 0;
356 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
356 virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
357 const VecElem& val) = 0;
358
357 const VecElem& val) = 0;
358
359 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0;
360 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0;
361 virtual void setVecPredRegFlat(int idx,
359 virtual const VecPredRegContainer &
360 readVecPredRegFlat(RegIndex idx) const = 0;
361 virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
362 virtual void setVecPredRegFlat(RegIndex idx,
362 const VecPredRegContainer& val) = 0;
363
363 const VecPredRegContainer& val) = 0;
364
364 virtual RegVal readCCRegFlat(int idx) = 0;
365 virtual void setCCRegFlat(int idx, RegVal val) = 0;
365 virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
366 virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
366 /** @} */
367
368};
369
367 /** @} */
368
369};
370
370/**
371 * ProxyThreadContext class that provides a way to implement a
372 * ThreadContext without having to derive from it. ThreadContext is an
373 * abstract class, so anything that derives from it and uses its
374 * interface will pay the overhead of virtual function calls. This
375 * class is created to enable a user-defined Thread object to be used
376 * wherever ThreadContexts are used, without paying the overhead of
377 * virtual function calls when it is used by itself. See
378 * simple_thread.hh for an example of this.
379 */
380template <class TC>
381class ProxyThreadContext : public ThreadContext
382{
383 public:
384 ProxyThreadContext(TC *actual_tc)
385 { actualTC = actual_tc; }
386
387 private:
388 TC *actualTC;
389
390 public:
391
392 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
393
394 int cpuId() const { return actualTC->cpuId(); }
395
396 uint32_t socketId() const { return actualTC->socketId(); }
397
398 int threadId() const { return actualTC->threadId(); }
399
400 void setThreadId(int id) { actualTC->setThreadId(id); }
401
402 int contextId() const { return actualTC->contextId(); }
403
404 void setContextId(int id) { actualTC->setContextId(id); }
405
406 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
407
408 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
409
410 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
411
412 TheISA::ISA *getIsaPtr() { return actualTC->getIsaPtr(); }
413
414 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
415
416 System *getSystemPtr() { return actualTC->getSystemPtr(); }
417
418 TheISA::Kernel::Statistics *getKernelStats()
419 { return actualTC->getKernelStats(); }
420
421 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
422
423 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
424
425 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
426
427 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
428
429 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
430
431 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
432
433 Status status() const { return actualTC->status(); }
434
435 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
436
437 /// Set the status to Active.
438 void activate() { actualTC->activate(); }
439
440 /// Set the status to Suspended.
441 void suspend() { actualTC->suspend(); }
442
443 /// Set the status to Halted.
444 void halt() { actualTC->halt(); }
445
446 /// Quiesce thread context
447 void quiesce() { actualTC->quiesce(); }
448
449 /// Quiesce, suspend, and schedule activate at resume
450 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
451
452 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
453
454 void takeOverFrom(ThreadContext *oldContext)
455 { actualTC->takeOverFrom(oldContext); }
456
457 void regStats(const std::string &name) { actualTC->regStats(name); }
458
459 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
460
461 Tick readLastActivate() { return actualTC->readLastActivate(); }
462 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
463
464 void profileClear() { return actualTC->profileClear(); }
465 void profileSample() { return actualTC->profileSample(); }
466
467 // @todo: Do I need this?
468 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
469
470 void clearArchRegs() { actualTC->clearArchRegs(); }
471
472 //
473 // New accessors for new decoder.
474 //
475 RegVal readIntReg(int reg_idx)
476 { return actualTC->readIntReg(reg_idx); }
477
478 RegVal readFloatReg(int reg_idx)
479 { return actualTC->readFloatReg(reg_idx); }
480
481 const VecRegContainer& readVecReg(const RegId& reg) const
482 { return actualTC->readVecReg(reg); }
483
484 VecRegContainer& getWritableVecReg(const RegId& reg)
485 { return actualTC->getWritableVecReg(reg); }
486
487 /** Vector Register Lane Interfaces. */
488 /** @{ */
489 /** Reads source vector 8bit operand. */
490 ConstVecLane8
491 readVec8BitLaneReg(const RegId& reg) const
492 { return actualTC->readVec8BitLaneReg(reg); }
493
494 /** Reads source vector 16bit operand. */
495 ConstVecLane16
496 readVec16BitLaneReg(const RegId& reg) const
497 { return actualTC->readVec16BitLaneReg(reg); }
498
499 /** Reads source vector 32bit operand. */
500 ConstVecLane32
501 readVec32BitLaneReg(const RegId& reg) const
502 { return actualTC->readVec32BitLaneReg(reg); }
503
504 /** Reads source vector 64bit operand. */
505 ConstVecLane64
506 readVec64BitLaneReg(const RegId& reg) const
507 { return actualTC->readVec64BitLaneReg(reg); }
508
509 /** Write a lane of the destination vector register. */
510 virtual void setVecLane(const RegId& reg,
511 const LaneData<LaneSize::Byte>& val)
512 { return actualTC->setVecLane(reg, val); }
513 virtual void setVecLane(const RegId& reg,
514 const LaneData<LaneSize::TwoByte>& val)
515 { return actualTC->setVecLane(reg, val); }
516 virtual void setVecLane(const RegId& reg,
517 const LaneData<LaneSize::FourByte>& val)
518 { return actualTC->setVecLane(reg, val); }
519 virtual void setVecLane(const RegId& reg,
520 const LaneData<LaneSize::EightByte>& val)
521 { return actualTC->setVecLane(reg, val); }
522 /** @} */
523
524 const VecElem& readVecElem(const RegId& reg) const
525 { return actualTC->readVecElem(reg); }
526
527 const VecPredRegContainer& readVecPredReg(const RegId& reg) const
528 { return actualTC->readVecPredReg(reg); }
529
530 VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
531 { return actualTC->getWritableVecPredReg(reg); }
532
533 RegVal readCCReg(int reg_idx)
534 { return actualTC->readCCReg(reg_idx); }
535
536 void setIntReg(int reg_idx, RegVal val)
537 { actualTC->setIntReg(reg_idx, val); }
538
539 void setFloatReg(int reg_idx, RegVal val)
540 { actualTC->setFloatReg(reg_idx, val); }
541
542 void setVecReg(const RegId& reg, const VecRegContainer& val)
543 { actualTC->setVecReg(reg, val); }
544
545 void setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
546 { actualTC->setVecPredReg(reg, val); }
547
548 void setVecElem(const RegId& reg, const VecElem& val)
549 { actualTC->setVecElem(reg, val); }
550
551 void setCCReg(int reg_idx, RegVal val)
552 { actualTC->setCCReg(reg_idx, val); }
553
554 TheISA::PCState pcState() { return actualTC->pcState(); }
555
556 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
557
558 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
559
560 Addr instAddr() { return actualTC->instAddr(); }
561 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
562 MicroPC microPC() { return actualTC->microPC(); }
563
564 bool readPredicate() { return actualTC->readPredicate(); }
565
566 void setPredicate(bool val)
567 { actualTC->setPredicate(val); }
568
569 RegVal readMiscRegNoEffect(int misc_reg) const
570 { return actualTC->readMiscRegNoEffect(misc_reg); }
571
572 RegVal readMiscReg(int misc_reg)
573 { return actualTC->readMiscReg(misc_reg); }
574
575 void setMiscRegNoEffect(int misc_reg, RegVal val)
576 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
577
578 void setMiscReg(int misc_reg, RegVal val)
579 { return actualTC->setMiscReg(misc_reg, val); }
580
581 RegId flattenRegId(const RegId& regId) const
582 { return actualTC->flattenRegId(regId); }
583
584 unsigned readStCondFailures()
585 { return actualTC->readStCondFailures(); }
586
587 void setStCondFailures(unsigned sc_failures)
588 { actualTC->setStCondFailures(sc_failures); }
589
590 void syscall(int64_t callnum, Fault *fault)
591 { actualTC->syscall(callnum, fault); }
592
593 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
594
595 RegVal readIntRegFlat(int idx)
596 { return actualTC->readIntRegFlat(idx); }
597
598 void setIntRegFlat(int idx, RegVal val)
599 { actualTC->setIntRegFlat(idx, val); }
600
601 RegVal readFloatRegFlat(int idx)
602 { return actualTC->readFloatRegFlat(idx); }
603
604 void setFloatRegFlat(int idx, RegVal val)
605 { actualTC->setFloatRegFlat(idx, val); }
606
607 const VecRegContainer& readVecRegFlat(int id) const
608 { return actualTC->readVecRegFlat(id); }
609
610 VecRegContainer& getWritableVecRegFlat(int id)
611 { return actualTC->getWritableVecRegFlat(id); }
612
613 void setVecRegFlat(int idx, const VecRegContainer& val)
614 { actualTC->setVecRegFlat(idx, val); }
615
616 const VecElem& readVecElemFlat(const RegIndex& id,
617 const ElemIndex& elemIndex) const
618 { return actualTC->readVecElemFlat(id, elemIndex); }
619
620 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
621 const VecElem& val)
622 { actualTC->setVecElemFlat(id, elemIndex, val); }
623
624 const VecPredRegContainer& readVecPredRegFlat(int id) const
625 { return actualTC->readVecPredRegFlat(id); }
626
627 VecPredRegContainer& getWritableVecPredRegFlat(int id)
628 { return actualTC->getWritableVecPredRegFlat(id); }
629
630 void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
631 { actualTC->setVecPredRegFlat(idx, val); }
632
633 RegVal readCCRegFlat(int idx)
634 { return actualTC->readCCRegFlat(idx); }
635
636 void setCCRegFlat(int idx, RegVal val)
637 { actualTC->setCCRegFlat(idx, val); }
638};
639
640/** @{ */
641/**
642 * Thread context serialization helpers
643 *
644 * These helper functions provide a way to the data in a
645 * ThreadContext. They are provided as separate helper function since
646 * implementing them as members of the ThreadContext interface would
647 * be confusing when the ThreadContext is exported via a proxy.
648 */
649
371/** @{ */
372/**
373 * Thread context serialization helpers
374 *
375 * These helper functions provide a way to the data in a
376 * ThreadContext. They are provided as separate helper function since
377 * implementing them as members of the ThreadContext interface would
378 * be confusing when the ThreadContext is exported via a proxy.
379 */
380
650void serialize(ThreadContext &tc, CheckpointOut &cp);
381void serialize(const ThreadContext &tc, CheckpointOut &cp);
651void unserialize(ThreadContext &tc, CheckpointIn &cp);
652
653/** @} */
654
655
656/**
657 * Copy state between thread contexts in preparation for CPU handover.
658 *
659 * @note This method modifies the old thread contexts as well as the
660 * new thread context. The old thread context will have its quiesce
661 * event descheduled if it is scheduled and its status set to halted.
662 *
663 * @param new_tc Destination ThreadContext.
664 * @param old_tc Source ThreadContext.
665 */
666void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
667
668#endif
382void unserialize(ThreadContext &tc, CheckpointIn &cp);
383
384/** @} */
385
386
387/**
388 * Copy state between thread contexts in preparation for CPU handover.
389 *
390 * @note This method modifies the old thread contexts as well as the
391 * new thread context. The old thread context will have its quiesce
392 * event descheduled if it is scheduled and its status set to halted.
393 *
394 * @param new_tc Destination ThreadContext.
395 * @param old_tc Source ThreadContext.
396 */
397void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
398
399#endif