thread_context.hh (13611:c8b7847b4171) thread_context.hh (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::CCReg CCReg;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
101 using VecPredRegContainer = TheISA::VecPredRegContainer;
102
103 public:
104
105 enum Status
106 {

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243 /** @} */
244
245 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
246
247 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
248 const = 0;
249 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
250
98 using VecRegContainer = TheISA::VecRegContainer;
99 using VecElem = TheISA::VecElem;
100 using VecPredRegContainer = TheISA::VecPredRegContainer;
101
102 public:
103
104 enum Status
105 {

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242 /** @} */
243
244 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
245
246 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
247 const = 0;
248 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
249
251 virtual CCReg readCCReg(int reg_idx) = 0;
250 virtual RegVal readCCReg(int reg_idx) = 0;
252
253 virtual void setIntReg(int reg_idx, RegVal val) = 0;
254
255 virtual void setFloatReg(int reg_idx, RegVal val) = 0;
256
257 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
258
259 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
260
261 virtual void setVecPredReg(const RegId& reg,
262 const VecPredRegContainer& val) = 0;
263
251
252 virtual void setIntReg(int reg_idx, RegVal val) = 0;
253
254 virtual void setFloatReg(int reg_idx, RegVal val) = 0;
255
256 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
257
258 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
259
260 virtual void setVecPredReg(const RegId& reg,
261 const VecPredRegContainer& val) = 0;
262
264 virtual void setCCReg(int reg_idx, CCReg val) = 0;
263 virtual void setCCReg(int reg_idx, RegVal val) = 0;
265
266 virtual TheISA::PCState pcState() = 0;
267
268 virtual void pcState(const TheISA::PCState &val) = 0;
269
270 void
271 setNPC(Addr val)
272 {

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350 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
351 const VecElem& val) = 0;
352
353 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0;
354 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0;
355 virtual void setVecPredRegFlat(int idx,
356 const VecPredRegContainer& val) = 0;
357
264
265 virtual TheISA::PCState pcState() = 0;
266
267 virtual void pcState(const TheISA::PCState &val) = 0;
268
269 void
270 setNPC(Addr val)
271 {

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349 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
350 const VecElem& val) = 0;
351
352 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0;
353 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0;
354 virtual void setVecPredRegFlat(int idx,
355 const VecPredRegContainer& val) = 0;
356
358 virtual CCReg readCCRegFlat(int idx) = 0;
359 virtual void setCCRegFlat(int idx, CCReg val) = 0;
357 virtual RegVal readCCRegFlat(int idx) = 0;
358 virtual void setCCRegFlat(int idx, RegVal val) = 0;
360 /** @} */
361
362};
363
364/**
365 * ProxyThreadContext class that provides a way to implement a
366 * ThreadContext without having to derive from it. ThreadContext is an
367 * abstract class, so anything that derives from it and uses its

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517 { return actualTC->readVecElem(reg); }
518
519 const VecPredRegContainer& readVecPredReg(const RegId& reg) const
520 { return actualTC->readVecPredReg(reg); }
521
522 VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
523 { return actualTC->getWritableVecPredReg(reg); }
524
359 /** @} */
360
361};
362
363/**
364 * ProxyThreadContext class that provides a way to implement a
365 * ThreadContext without having to derive from it. ThreadContext is an
366 * abstract class, so anything that derives from it and uses its

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516 { return actualTC->readVecElem(reg); }
517
518 const VecPredRegContainer& readVecPredReg(const RegId& reg) const
519 { return actualTC->readVecPredReg(reg); }
520
521 VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
522 { return actualTC->getWritableVecPredReg(reg); }
523
525 CCReg readCCReg(int reg_idx)
524 RegVal readCCReg(int reg_idx)
526 { return actualTC->readCCReg(reg_idx); }
527
528 void setIntReg(int reg_idx, RegVal val)
529 { actualTC->setIntReg(reg_idx, val); }
530
531 void setFloatReg(int reg_idx, RegVal val)
532 { actualTC->setFloatReg(reg_idx, val); }
533
534 void setVecReg(const RegId& reg, const VecRegContainer& val)
535 { actualTC->setVecReg(reg, val); }
536
537 void setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
538 { actualTC->setVecPredReg(reg, val); }
539
540 void setVecElem(const RegId& reg, const VecElem& val)
541 { actualTC->setVecElem(reg, val); }
542
525 { return actualTC->readCCReg(reg_idx); }
526
527 void setIntReg(int reg_idx, RegVal val)
528 { actualTC->setIntReg(reg_idx, val); }
529
530 void setFloatReg(int reg_idx, RegVal val)
531 { actualTC->setFloatReg(reg_idx, val); }
532
533 void setVecReg(const RegId& reg, const VecRegContainer& val)
534 { actualTC->setVecReg(reg, val); }
535
536 void setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
537 { actualTC->setVecPredReg(reg, val); }
538
539 void setVecElem(const RegId& reg, const VecElem& val)
540 { actualTC->setVecElem(reg, val); }
541
543 void setCCReg(int reg_idx, CCReg val)
542 void setCCReg(int reg_idx, RegVal val)
544 { actualTC->setCCReg(reg_idx, val); }
545
546 TheISA::PCState pcState() { return actualTC->pcState(); }
547
548 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
549
550 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
551

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617 { return actualTC->readVecPredRegFlat(id); }
618
619 VecPredRegContainer& getWritableVecPredRegFlat(int id)
620 { return actualTC->getWritableVecPredRegFlat(id); }
621
622 void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
623 { actualTC->setVecPredRegFlat(idx, val); }
624
543 { actualTC->setCCReg(reg_idx, val); }
544
545 TheISA::PCState pcState() { return actualTC->pcState(); }
546
547 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
548
549 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
550

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616 { return actualTC->readVecPredRegFlat(id); }
617
618 VecPredRegContainer& getWritableVecPredRegFlat(int id)
619 { return actualTC->getWritableVecPredRegFlat(id); }
620
621 void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
622 { actualTC->setVecPredRegFlat(idx, val); }
623
625 CCReg readCCRegFlat(int idx)
624 RegVal readCCRegFlat(int idx)
626 { return actualTC->readCCRegFlat(idx); }
627
625 { return actualTC->readCCRegFlat(idx); }
626
628 void setCCRegFlat(int idx, CCReg val)
627 void setCCRegFlat(int idx, RegVal val)
629 { actualTC->setCCRegFlat(idx, val); }
630};
631
632/** @{ */
633/**
634 * Thread context serialization helpers
635 *
636 * These helper functions provide a way to the data in a

--- 24 unchanged lines hidden --- 		628 { actualTC->setCCRegFlat(idx, val); }
629};
630
631/** @{ */
632/**
633 * Thread context serialization helpers
634 *
635 * These helper functions provide a way to the data in a

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