thread_context.hh (13582:989577bf6abc) thread_context.hh (13610:5d5404ac6288)
1/*
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::CCReg CCReg;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::CCReg CCReg;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
101 using VecPredRegContainer = TheISA::VecPredRegContainer;
102
101 public:
102
103 enum Status
104 {
105 /// Running. Instructions should be executed only when
106 /// the context is in this state.
107 Active,
108

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237 virtual void setVecLane(const RegId& reg,
238 const LaneData<LaneSize::FourByte>& val) = 0;
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::EightByte>& val) = 0;
241 /** @} */
242
243 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
244
103 public:
104
105 enum Status
106 {
107 /// Running. Instructions should be executed only when
108 /// the context is in this state.
109 Active,
110

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239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::FourByte>& val) = 0;
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::EightByte>& val) = 0;
243 /** @} */
244
245 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
246
247 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
248 const = 0;
249 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
250
245 virtual CCReg readCCReg(int reg_idx) = 0;
246
247 virtual void setIntReg(int reg_idx, RegVal val) = 0;
248
249 virtual void setFloatRegBits(int reg_idx, RegVal val) = 0;
250
251 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
252
253 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
254
251 virtual CCReg readCCReg(int reg_idx) = 0;
252
253 virtual void setIntReg(int reg_idx, RegVal val) = 0;
254
255 virtual void setFloatRegBits(int reg_idx, RegVal val) = 0;
256
257 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
258
259 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
260
261 virtual void setVecPredReg(const RegId& reg,
262 const VecPredRegContainer& val) = 0;
263
255 virtual void setCCReg(int reg_idx, CCReg val) = 0;
256
257 virtual TheISA::PCState pcState() = 0;
258
259 virtual void pcState(const TheISA::PCState &val) = 0;
260
261 void
262 setNPC(Addr val)

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336 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
337 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
338
339 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
340 const ElemIndex& elemIdx) const = 0;
341 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
342 const VecElem& val) = 0;
343
264 virtual void setCCReg(int reg_idx, CCReg val) = 0;
265
266 virtual TheISA::PCState pcState() = 0;
267
268 virtual void pcState(const TheISA::PCState &val) = 0;
269
270 void
271 setNPC(Addr val)

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345 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
346 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
347
348 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
349 const ElemIndex& elemIdx) const = 0;
350 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
351 const VecElem& val) = 0;
352
353 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0;
354 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0;
355 virtual void setVecPredRegFlat(int idx,
356 const VecPredRegContainer& val) = 0;
357
344 virtual CCReg readCCRegFlat(int idx) = 0;
345 virtual void setCCRegFlat(int idx, CCReg val) = 0;
346 /** @} */
347
348};
349
350/**
351 * ProxyThreadContext class that provides a way to implement a

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497 virtual void setVecLane(const RegId& reg,
498 const LaneData<LaneSize::EightByte>& val)
499 { return actualTC->setVecLane(reg, val); }
500 /** @} */
501
502 const VecElem& readVecElem(const RegId& reg) const
503 { return actualTC->readVecElem(reg); }
504
358 virtual CCReg readCCRegFlat(int idx) = 0;
359 virtual void setCCRegFlat(int idx, CCReg val) = 0;
360 /** @} */
361
362};
363
364/**
365 * ProxyThreadContext class that provides a way to implement a

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511 virtual void setVecLane(const RegId& reg,
512 const LaneData<LaneSize::EightByte>& val)
513 { return actualTC->setVecLane(reg, val); }
514 /** @} */
515
516 const VecElem& readVecElem(const RegId& reg) const
517 { return actualTC->readVecElem(reg); }
518
519 const VecPredRegContainer& readVecPredReg(const RegId& reg) const
520 { return actualTC->readVecPredReg(reg); }
521
522 VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
523 { return actualTC->getWritableVecPredReg(reg); }
524
505 CCReg readCCReg(int reg_idx)
506 { return actualTC->readCCReg(reg_idx); }
507
508 void setIntReg(int reg_idx, RegVal val)
509 { actualTC->setIntReg(reg_idx, val); }
510
511 void setFloatRegBits(int reg_idx, RegVal val)
512 { actualTC->setFloatRegBits(reg_idx, val); }
513
514 void setVecReg(const RegId& reg, const VecRegContainer& val)
515 { actualTC->setVecReg(reg, val); }
516
525 CCReg readCCReg(int reg_idx)
526 { return actualTC->readCCReg(reg_idx); }
527
528 void setIntReg(int reg_idx, RegVal val)
529 { actualTC->setIntReg(reg_idx, val); }
530
531 void setFloatRegBits(int reg_idx, RegVal val)
532 { actualTC->setFloatRegBits(reg_idx, val); }
533
534 void setVecReg(const RegId& reg, const VecRegContainer& val)
535 { actualTC->setVecReg(reg, val); }
536
537 void setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
538 { actualTC->setVecPredReg(reg, val); }
539
517 void setVecElem(const RegId& reg, const VecElem& val)
518 { actualTC->setVecElem(reg, val); }
519
520 void setCCReg(int reg_idx, CCReg val)
521 { actualTC->setCCReg(reg_idx, val); }
522
523 TheISA::PCState pcState() { return actualTC->pcState(); }
524

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585 const VecElem& readVecElemFlat(const RegIndex& id,
586 const ElemIndex& elemIndex) const
587 { return actualTC->readVecElemFlat(id, elemIndex); }
588
589 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
590 const VecElem& val)
591 { actualTC->setVecElemFlat(id, elemIndex, val); }
592
540 void setVecElem(const RegId& reg, const VecElem& val)
541 { actualTC->setVecElem(reg, val); }
542
543 void setCCReg(int reg_idx, CCReg val)
544 { actualTC->setCCReg(reg_idx, val); }
545
546 TheISA::PCState pcState() { return actualTC->pcState(); }
547

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608 const VecElem& readVecElemFlat(const RegIndex& id,
609 const ElemIndex& elemIndex) const
610 { return actualTC->readVecElemFlat(id, elemIndex); }
611
612 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
613 const VecElem& val)
614 { actualTC->setVecElemFlat(id, elemIndex, val); }
615
616 const VecPredRegContainer& readVecPredRegFlat(int id) const
617 { return actualTC->readVecPredRegFlat(id); }
618
619 VecPredRegContainer& getWritableVecPredRegFlat(int id)
620 { return actualTC->getWritableVecPredRegFlat(id); }
621
622 void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
623 { actualTC->setVecPredRegFlat(idx, val); }
624
593 CCReg readCCRegFlat(int idx)
594 { return actualTC->readCCRegFlat(idx); }
595
596 void setCCRegFlat(int idx, CCReg val)
597 { actualTC->setCCRegFlat(idx, val); }
598};
599
600/** @{ */

--- 28 unchanged lines hidden --- 		625 CCReg readCCRegFlat(int idx)
626 { return actualTC->readCCRegFlat(idx); }
627
628 void setCCRegFlat(int idx, CCReg val)
629 { actualTC->setCCRegFlat(idx, val); }
630};
631
632/** @{ */

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