thread_context.hh (12106:7784fac1b159) thread_context.hh (12109:f29e9c5418aa)
1/*
1/*
2 * Copyright (c) 2011-2012 ARM Limited
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::IntReg IntReg;
99 typedef TheISA::FloatReg FloatReg;
100 typedef TheISA::FloatRegBits FloatRegBits;
101 typedef TheISA::CCReg CCReg;
102 typedef TheISA::MiscReg MiscReg;
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::IntReg IntReg;
99 typedef TheISA::FloatReg FloatReg;
100 typedef TheISA::FloatRegBits FloatRegBits;
101 typedef TheISA::CCReg CCReg;
102 typedef TheISA::MiscReg MiscReg;
103 using VecRegContainer = TheISA::VecRegContainer;
104 using VecElem = TheISA::VecElem;
103 public:
104
105 enum Status
106 {
107 /// Running. Instructions should be executed only when
108 /// the context is in this state.
109 Active,
110

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207 // New accessors for new decoder.
208 //
209 virtual uint64_t readIntReg(int reg_idx) = 0;
210
211 virtual FloatReg readFloatReg(int reg_idx) = 0;
212
213 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
214
105 public:
106
107 enum Status
108 {
109 /// Running. Instructions should be executed only when
110 /// the context is in this state.
111 Active,
112

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209 // New accessors for new decoder.
210 //
211 virtual uint64_t readIntReg(int reg_idx) = 0;
212
213 virtual FloatReg readFloatReg(int reg_idx) = 0;
214
215 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
216
217 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
218 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
219
220 /** Vector Register Lane Interfaces. */
221 /** @{ */
222 /** Reads source vector 8bit operand. */
223 virtual ConstVecLane8
224 readVec8BitLaneReg(const RegId& reg) const = 0;
225
226 /** Reads source vector 16bit operand. */
227 virtual ConstVecLane16
228 readVec16BitLaneReg(const RegId& reg) const = 0;
229
230 /** Reads source vector 32bit operand. */
231 virtual ConstVecLane32
232 readVec32BitLaneReg(const RegId& reg) const = 0;
233
234 /** Reads source vector 64bit operand. */
235 virtual ConstVecLane64
236 readVec64BitLaneReg(const RegId& reg) const = 0;
237
238 /** Write a lane of the destination vector register. */
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::Byte>& val) = 0;
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::TwoByte>& val) = 0;
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::FourByte>& val) = 0;
245 virtual void setVecLane(const RegId& reg,
246 const LaneData<LaneSize::EightByte>& val) = 0;
247 /** @} */
248
249 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
250
215 virtual CCReg readCCReg(int reg_idx) = 0;
216
217 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
218
219 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
220
221 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
222
251 virtual CCReg readCCReg(int reg_idx) = 0;
252
253 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
254
255 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
256
257 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
258
259 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
260
261 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
262
223 virtual void setCCReg(int reg_idx, CCReg val) = 0;
224
225 virtual TheISA::PCState pcState() = 0;
226
227 virtual void pcState(const TheISA::PCState &val) = 0;
228
229 void
230 setNPC(Addr val)

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298 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
299
300 virtual FloatReg readFloatRegFlat(int idx) = 0;
301 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
302
303 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
304 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
305
263 virtual void setCCReg(int reg_idx, CCReg val) = 0;
264
265 virtual TheISA::PCState pcState() = 0;
266
267 virtual void pcState(const TheISA::PCState &val) = 0;
268
269 void
270 setNPC(Addr val)

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338 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
339
340 virtual FloatReg readFloatRegFlat(int idx) = 0;
341 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
342
343 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
344 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
345
346 virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
347 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
348 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
349
350 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
351 const ElemIndex& elemIdx) const = 0;
352 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
353 const VecElem& val) = 0;
354
306 virtual CCReg readCCRegFlat(int idx) = 0;
307 virtual void setCCRegFlat(int idx, CCReg val) = 0;
308 /** @} */
309
310};
311
312/**
313 * ProxyThreadContext class that provides a way to implement a

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416 { return actualTC->readIntReg(reg_idx); }
417
418 FloatReg readFloatReg(int reg_idx)
419 { return actualTC->readFloatReg(reg_idx); }
420
421 FloatRegBits readFloatRegBits(int reg_idx)
422 { return actualTC->readFloatRegBits(reg_idx); }
423
355 virtual CCReg readCCRegFlat(int idx) = 0;
356 virtual void setCCRegFlat(int idx, CCReg val) = 0;
357 /** @} */
358
359};
360
361/**
362 * ProxyThreadContext class that provides a way to implement a

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465 { return actualTC->readIntReg(reg_idx); }
466
467 FloatReg readFloatReg(int reg_idx)
468 { return actualTC->readFloatReg(reg_idx); }
469
470 FloatRegBits readFloatRegBits(int reg_idx)
471 { return actualTC->readFloatRegBits(reg_idx); }
472
473 const VecRegContainer& readVecReg(const RegId& reg) const
474 { return actualTC->readVecReg(reg); }
475
476 VecRegContainer& getWritableVecReg(const RegId& reg)
477 { return actualTC->getWritableVecReg(reg); }
478
479 /** Vector Register Lane Interfaces. */
480 /** @{ */
481 /** Reads source vector 8bit operand. */
482 ConstVecLane8
483 readVec8BitLaneReg(const RegId& reg) const
484 { return actualTC->readVec8BitLaneReg(reg); }
485
486 /** Reads source vector 16bit operand. */
487 ConstVecLane16
488 readVec16BitLaneReg(const RegId& reg) const
489 { return actualTC->readVec16BitLaneReg(reg); }
490
491 /** Reads source vector 32bit operand. */
492 ConstVecLane32
493 readVec32BitLaneReg(const RegId& reg) const
494 { return actualTC->readVec32BitLaneReg(reg); }
495
496 /** Reads source vector 64bit operand. */
497 ConstVecLane64
498 readVec64BitLaneReg(const RegId& reg) const
499 { return actualTC->readVec64BitLaneReg(reg); }
500
501 /** Write a lane of the destination vector register. */
502 virtual void setVecLane(const RegId& reg,
503 const LaneData<LaneSize::Byte>& val)
504 { return actualTC->setVecLane(reg, val); }
505 virtual void setVecLane(const RegId& reg,
506 const LaneData<LaneSize::TwoByte>& val)
507 { return actualTC->setVecLane(reg, val); }
508 virtual void setVecLane(const RegId& reg,
509 const LaneData<LaneSize::FourByte>& val)
510 { return actualTC->setVecLane(reg, val); }
511 virtual void setVecLane(const RegId& reg,
512 const LaneData<LaneSize::EightByte>& val)
513 { return actualTC->setVecLane(reg, val); }
514 /** @} */
515
516 const VecElem& readVecElem(const RegId& reg) const
517 { return actualTC->readVecElem(reg); }
518
424 CCReg readCCReg(int reg_idx)
425 { return actualTC->readCCReg(reg_idx); }
426
427 void setIntReg(int reg_idx, uint64_t val)
428 { actualTC->setIntReg(reg_idx, val); }
429
430 void setFloatReg(int reg_idx, FloatReg val)
431 { actualTC->setFloatReg(reg_idx, val); }
432
433 void setFloatRegBits(int reg_idx, FloatRegBits val)
434 { actualTC->setFloatRegBits(reg_idx, val); }
435
519 CCReg readCCReg(int reg_idx)
520 { return actualTC->readCCReg(reg_idx); }
521
522 void setIntReg(int reg_idx, uint64_t val)
523 { actualTC->setIntReg(reg_idx, val); }
524
525 void setFloatReg(int reg_idx, FloatReg val)
526 { actualTC->setFloatReg(reg_idx, val); }
527
528 void setFloatRegBits(int reg_idx, FloatRegBits val)
529 { actualTC->setFloatRegBits(reg_idx, val); }
530
531 void setVecReg(const RegId& reg, const VecRegContainer& val)
532 { actualTC->setVecReg(reg, val); }
533
534 void setVecElem(const RegId& reg, const VecElem& val)
535 { actualTC->setVecElem(reg, val); }
536
436 void setCCReg(int reg_idx, CCReg val)
437 { actualTC->setCCReg(reg_idx, val); }
438
439 TheISA::PCState pcState() { return actualTC->pcState(); }
440
441 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
442
443 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }

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490 { actualTC->setFloatRegFlat(idx, val); }
491
492 FloatRegBits readFloatRegBitsFlat(int idx)
493 { return actualTC->readFloatRegBitsFlat(idx); }
494
495 void setFloatRegBitsFlat(int idx, FloatRegBits val)
496 { actualTC->setFloatRegBitsFlat(idx, val); }
497
537 void setCCReg(int reg_idx, CCReg val)
538 { actualTC->setCCReg(reg_idx, val); }
539
540 TheISA::PCState pcState() { return actualTC->pcState(); }
541
542 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
543
544 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }

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591 { actualTC->setFloatRegFlat(idx, val); }
592
593 FloatRegBits readFloatRegBitsFlat(int idx)
594 { return actualTC->readFloatRegBitsFlat(idx); }
595
596 void setFloatRegBitsFlat(int idx, FloatRegBits val)
597 { actualTC->setFloatRegBitsFlat(idx, val); }
598
599 const VecRegContainer& readVecRegFlat(int id) const
600 { return actualTC->readVecRegFlat(id); }
601
602 VecRegContainer& getWritableVecRegFlat(int id)
603 { return actualTC->getWritableVecRegFlat(id); }
604
605 void setVecRegFlat(int idx, const VecRegContainer& val)
606 { actualTC->setVecRegFlat(idx, val); }
607
608 const VecElem& readVecElemFlat(const RegIndex& id,
609 const ElemIndex& elemIndex) const
610 { return actualTC->readVecElemFlat(id, elemIndex); }
611
612 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
613 const VecElem& val)
614 { actualTC->setVecElemFlat(id, elemIndex, val); }
615
498 CCReg readCCRegFlat(int idx)
499 { return actualTC->readCCRegFlat(idx); }
500
501 void setCCRegFlat(int idx, CCReg val)
502 { actualTC->setCCRegFlat(idx, val); }
503};
504
505/** @{ */

--- 28 unchanged lines hidden --- 		616 CCReg readCCRegFlat(int idx)
617 { return actualTC->readCCRegFlat(idx); }
618
619 void setCCRegFlat(int idx, CCReg val)
620 { actualTC->setCCRegFlat(idx, val); }
621};
622
623/** @{ */

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