thread_context.hh (12104:edd63f9c6184) thread_context.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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245 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
246
247 virtual MiscReg readMiscReg(int misc_reg) = 0;
248
249 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
250
251 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
252
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 236 unchanged lines hidden (view full) ---

245 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
246
247 virtual MiscReg readMiscReg(int misc_reg) = 0;
248
249 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
250
251 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
252
253 virtual int flattenIntIndex(int reg) = 0;
254 virtual int flattenFloatIndex(int reg) = 0;
255 virtual int flattenCCIndex(int reg) = 0;
256 virtual int flattenMiscIndex(int reg) = 0;
253 virtual RegId flattenRegId(const RegId& regId) const = 0;
257
258 virtual uint64_t
254
255 virtual uint64_t
259 readRegOtherThread(RegId misc_reg, ThreadID tid)
256 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
260 {
261 return 0;
262 }
263
264 virtual void
257 {
258 return 0;
259 }
260
261 virtual void
265 setRegOtherThread(RegId misc_reg, const MiscReg &val, ThreadID tid)
262 setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid)
266 {
267 }
268
269 // Also not necessarily the best location for these two. Hopefully will go
270 // away once we decide upon where st cond failures goes.
271 virtual unsigned readStCondFailures() = 0;
272
273 virtual void setStCondFailures(unsigned sc_failures) = 0;

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286 static void compare(ThreadContext *one, ThreadContext *two);
287
288 /** @{ */
289 /**
290 * Flat register interfaces
291 *
292 * Some architectures have different registers visible in
293 * different modes. Such architectures "flatten" a register (see
263 {
264 }
265
266 // Also not necessarily the best location for these two. Hopefully will go
267 // away once we decide upon where st cond failures goes.
268 virtual unsigned readStCondFailures() = 0;
269
270 virtual void setStCondFailures(unsigned sc_failures) = 0;

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283 static void compare(ThreadContext *one, ThreadContext *two);
284
285 /** @{ */
286 /**
287 * Flat register interfaces
288 *
289 * Some architectures have different registers visible in
290 * different modes. Such architectures "flatten" a register (see
294 * flattenIntIndex() and flattenFloatIndex()) to map it into the
291 * flattenRegId()) to map it into the
295 * gem5 register file. This interface provides a flat interface to
296 * the underlying register file, which allows for example
297 * serialization code to access all registers.
298 */
299
300 virtual uint64_t readIntRegFlat(int idx) = 0;
301 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
302

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461 { return actualTC->readMiscReg(misc_reg); }
462
463 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
464 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
465
466 void setMiscReg(int misc_reg, const MiscReg &val)
467 { return actualTC->setMiscReg(misc_reg, val); }
468
292 * gem5 register file. This interface provides a flat interface to
293 * the underlying register file, which allows for example
294 * serialization code to access all registers.
295 */
296
297 virtual uint64_t readIntRegFlat(int idx) = 0;
298 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
299

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458 { return actualTC->readMiscReg(misc_reg); }
459
460 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
461 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
462
463 void setMiscReg(int misc_reg, const MiscReg &val)
464 { return actualTC->setMiscReg(misc_reg, val); }
465
469 int flattenIntIndex(int reg)
470 { return actualTC->flattenIntIndex(reg); }
466 RegId flattenRegId(const RegId& regId) const
467 { return actualTC->flattenRegId(regId); }
471
468
472 int flattenFloatIndex(int reg)
473 { return actualTC->flattenFloatIndex(reg); }
474
475 int flattenCCIndex(int reg)
476 { return actualTC->flattenCCIndex(reg); }
477
478 int flattenMiscIndex(int reg)
479 { return actualTC->flattenMiscIndex(reg); }
480
481 unsigned readStCondFailures()
482 { return actualTC->readStCondFailures(); }
483
484 void setStCondFailures(unsigned sc_failures)
485 { actualTC->setStCondFailures(sc_failures); }
486
487 void syscall(int64_t callnum, Fault *fault)
488 { actualTC->syscall(callnum, fault); }

--- 57 unchanged lines hidden --- 		469 unsigned readStCondFailures()
470 { return actualTC->readStCondFailures(); }
471
472 void setStCondFailures(unsigned sc_failures)
473 { actualTC->setStCondFailures(sc_failures); }
474
475 void syscall(int64_t callnum, Fault *fault)
476 { actualTC->syscall(callnum, fault); }

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