thread_context.hh (10934:5af8f40d8f2c) thread_context.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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93class ThreadContext
94{
95 protected:
96 typedef TheISA::MachInst MachInst;
97 typedef TheISA::IntReg IntReg;
98 typedef TheISA::FloatReg FloatReg;
99 typedef TheISA::FloatRegBits FloatRegBits;
100 typedef TheISA::CCReg CCReg;
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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93class ThreadContext
94{
95 protected:
96 typedef TheISA::MachInst MachInst;
97 typedef TheISA::IntReg IntReg;
98 typedef TheISA::FloatReg FloatReg;
99 typedef TheISA::FloatRegBits FloatRegBits;
100 typedef TheISA::CCReg CCReg;
101 typedef TheISA::VectorReg VectorReg;
102 typedef TheISA::MiscReg MiscReg;
103 public:
104
105 enum Status
106 {
107 /// Running. Instructions should be executed only when
108 /// the context is in this state.
109 Active,

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201 virtual uint64_t readIntReg(int reg_idx) = 0;
202
203 virtual FloatReg readFloatReg(int reg_idx) = 0;
204
205 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
206
207 virtual CCReg readCCReg(int reg_idx) = 0;
208
101 typedef TheISA::MiscReg MiscReg;
102 public:
103
104 enum Status
105 {
106 /// Running. Instructions should be executed only when
107 /// the context is in this state.
108 Active,

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200 virtual uint64_t readIntReg(int reg_idx) = 0;
201
202 virtual FloatReg readFloatReg(int reg_idx) = 0;
203
204 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
205
206 virtual CCReg readCCReg(int reg_idx) = 0;
207
209 virtual const VectorReg &readVectorReg(int reg_idx) = 0;
210
211 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
212
213 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
214
215 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
216
217 virtual void setCCReg(int reg_idx, CCReg val) = 0;
218
208 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
209
210 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
211
212 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
213
214 virtual void setCCReg(int reg_idx, CCReg val) = 0;
215
219 virtual void setVectorReg(int reg_idx, const VectorReg &val) = 0;
220
221 virtual TheISA::PCState pcState() = 0;
222
223 virtual void pcState(const TheISA::PCState &val) = 0;
224
225 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
226
227 virtual Addr instAddr() = 0;
228

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236
237 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
238
239 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
240
241 virtual int flattenIntIndex(int reg) = 0;
242 virtual int flattenFloatIndex(int reg) = 0;
243 virtual int flattenCCIndex(int reg) = 0;
216 virtual TheISA::PCState pcState() = 0;
217
218 virtual void pcState(const TheISA::PCState &val) = 0;
219
220 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
221
222 virtual Addr instAddr() = 0;
223

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231
232 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
233
234 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
235
236 virtual int flattenIntIndex(int reg) = 0;
237 virtual int flattenFloatIndex(int reg) = 0;
238 virtual int flattenCCIndex(int reg) = 0;
244 virtual int flattenVectorIndex(int reg) = 0;
245 virtual int flattenMiscIndex(int reg) = 0;
246
247 virtual uint64_t
248 readRegOtherThread(int misc_reg, ThreadID tid)
249 {
250 return 0;
251 }
252

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292 virtual FloatReg readFloatRegFlat(int idx) = 0;
293 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
294
295 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
296 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
297
298 virtual CCReg readCCRegFlat(int idx) = 0;
299 virtual void setCCRegFlat(int idx, CCReg val) = 0;
239 virtual int flattenMiscIndex(int reg) = 0;
240
241 virtual uint64_t
242 readRegOtherThread(int misc_reg, ThreadID tid)
243 {
244 return 0;
245 }
246

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286 virtual FloatReg readFloatRegFlat(int idx) = 0;
287 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
288
289 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
290 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
291
292 virtual CCReg readCCRegFlat(int idx) = 0;
293 virtual void setCCRegFlat(int idx, CCReg val) = 0;
300
301 virtual const VectorReg &readVectorRegFlat(int idx) = 0;
302 virtual void setVectorRegFlat(int idx, const VectorReg &val) = 0;
303 /** @} */
304
305};
306
307/**
308 * ProxyThreadContext class that provides a way to implement a
309 * ThreadContext without having to derive from it. ThreadContext is an
310 * abstract class, so anything that derives from it and uses its

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406 { return actualTC->readFloatReg(reg_idx); }
407
408 FloatRegBits readFloatRegBits(int reg_idx)
409 { return actualTC->readFloatRegBits(reg_idx); }
410
411 CCReg readCCReg(int reg_idx)
412 { return actualTC->readCCReg(reg_idx); }
413
294 /** @} */
295
296};
297
298/**
299 * ProxyThreadContext class that provides a way to implement a
300 * ThreadContext without having to derive from it. ThreadContext is an
301 * abstract class, so anything that derives from it and uses its

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397 { return actualTC->readFloatReg(reg_idx); }
398
399 FloatRegBits readFloatRegBits(int reg_idx)
400 { return actualTC->readFloatRegBits(reg_idx); }
401
402 CCReg readCCReg(int reg_idx)
403 { return actualTC->readCCReg(reg_idx); }
404
414 const VectorReg &readVectorReg(int reg_idx)
415 { return actualTC->readVectorReg(reg_idx); }
416
417 void setIntReg(int reg_idx, uint64_t val)
418 { actualTC->setIntReg(reg_idx, val); }
419
420 void setFloatReg(int reg_idx, FloatReg val)
421 { actualTC->setFloatReg(reg_idx, val); }
422
423 void setFloatRegBits(int reg_idx, FloatRegBits val)
424 { actualTC->setFloatRegBits(reg_idx, val); }
425
426 void setCCReg(int reg_idx, CCReg val)
427 { actualTC->setCCReg(reg_idx, val); }
428
405 void setIntReg(int reg_idx, uint64_t val)
406 { actualTC->setIntReg(reg_idx, val); }
407
408 void setFloatReg(int reg_idx, FloatReg val)
409 { actualTC->setFloatReg(reg_idx, val); }
410
411 void setFloatRegBits(int reg_idx, FloatRegBits val)
412 { actualTC->setFloatRegBits(reg_idx, val); }
413
414 void setCCReg(int reg_idx, CCReg val)
415 { actualTC->setCCReg(reg_idx, val); }
416
429 void setVectorReg(int reg_idx, const VectorReg &val)
430 { actualTC->setVectorReg(reg_idx, val); }
431
432 TheISA::PCState pcState() { return actualTC->pcState(); }
433
434 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
435
436 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
437
438 Addr instAddr() { return actualTC->instAddr(); }
439 Addr nextInstAddr() { return actualTC->nextInstAddr(); }

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460 { return actualTC->flattenIntIndex(reg); }
461
462 int flattenFloatIndex(int reg)
463 { return actualTC->flattenFloatIndex(reg); }
464
465 int flattenCCIndex(int reg)
466 { return actualTC->flattenCCIndex(reg); }
467
417 TheISA::PCState pcState() { return actualTC->pcState(); }
418
419 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
420
421 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
422
423 Addr instAddr() { return actualTC->instAddr(); }
424 Addr nextInstAddr() { return actualTC->nextInstAddr(); }

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445 { return actualTC->flattenIntIndex(reg); }
446
447 int flattenFloatIndex(int reg)
448 { return actualTC->flattenFloatIndex(reg); }
449
450 int flattenCCIndex(int reg)
451 { return actualTC->flattenCCIndex(reg); }
452
468 int flattenVectorIndex(int reg)
469 { return actualTC->flattenVectorIndex(reg); }
470
471 int flattenMiscIndex(int reg)
472 { return actualTC->flattenMiscIndex(reg); }
473
474 unsigned readStCondFailures()
475 { return actualTC->readStCondFailures(); }
476
477 void setStCondFailures(unsigned sc_failures)
478 { actualTC->setStCondFailures(sc_failures); }

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500 void setFloatRegBitsFlat(int idx, FloatRegBits val)
501 { actualTC->setFloatRegBitsFlat(idx, val); }
502
503 CCReg readCCRegFlat(int idx)
504 { return actualTC->readCCRegFlat(idx); }
505
506 void setCCRegFlat(int idx, CCReg val)
507 { actualTC->setCCRegFlat(idx, val); }
453 int flattenMiscIndex(int reg)
454 { return actualTC->flattenMiscIndex(reg); }
455
456 unsigned readStCondFailures()
457 { return actualTC->readStCondFailures(); }
458
459 void setStCondFailures(unsigned sc_failures)
460 { actualTC->setStCondFailures(sc_failures); }

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482 void setFloatRegBitsFlat(int idx, FloatRegBits val)
483 { actualTC->setFloatRegBitsFlat(idx, val); }
484
485 CCReg readCCRegFlat(int idx)
486 { return actualTC->readCCRegFlat(idx); }
487
488 void setCCRegFlat(int idx, CCReg val)
489 { actualTC->setCCRegFlat(idx, val); }
508
509 const VectorReg &readVectorRegFlat(int idx)
510 { return actualTC->readVectorRegFlat(idx); }
511
512 void setVectorRegFlat(int idx, const VectorReg &val)
513 { actualTC->setVectorRegFlat(idx, val); }
514};
515
516/** @{ */
517/**
518 * Thread context serialization helpers
519 *
520 * These helper functions provide a way to the data in a
521 * ThreadContext. They are provided as separate helper function since

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491
492/** @{ */
493/**
494 * Thread context serialization helpers
495 *
496 * These helper functions provide a way to the data in a
497 * ThreadContext. They are provided as separate helper function since

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