| thread_context.hh (10664:61a0b02aa800) | thread_context.hh (10698:829adc48e175) |
|---|---|
| 1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 211 unchanged lines hidden (view full) --- 220 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 221 222 virtual Addr instAddr() = 0; 223 224 virtual Addr nextInstAddr() = 0; 225 226 virtual MicroPC microPC() = 0; 227 | 1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 211 unchanged lines hidden (view full) --- 220 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 221 222 virtual Addr instAddr() = 0; 223 224 virtual Addr nextInstAddr() = 0; 225 226 virtual MicroPC microPC() = 0; 227 |
| 228 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; | 228 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0; |
| 229 230 virtual MiscReg readMiscReg(int misc_reg) = 0; 231 232 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 233 234 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 235 236 virtual int flattenIntIndex(int reg) = 0; --- 187 unchanged lines hidden (view full) --- 424 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 425 MicroPC microPC() { return actualTC->microPC(); } 426 427 bool readPredicate() { return actualTC->readPredicate(); } 428 429 void setPredicate(bool val) 430 { actualTC->setPredicate(val); } 431 | 229 230 virtual MiscReg readMiscReg(int misc_reg) = 0; 231 232 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 233 234 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 235 236 virtual int flattenIntIndex(int reg) = 0; --- 187 unchanged lines hidden (view full) --- 424 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 425 MicroPC microPC() { return actualTC->microPC(); } 426 427 bool readPredicate() { return actualTC->readPredicate(); } 428 429 void setPredicate(bool val) 430 { actualTC->setPredicate(val); } 431 |
| 432 MiscReg readMiscRegNoEffect(int misc_reg) | 432 MiscReg readMiscRegNoEffect(int misc_reg) const |
| 433 { return actualTC->readMiscRegNoEffect(misc_reg); } 434 435 MiscReg readMiscReg(int misc_reg) 436 { return actualTC->readMiscReg(misc_reg); } 437 438 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 439 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 440 --- 80 unchanged lines hidden --- | 433 { return actualTC->readMiscRegNoEffect(misc_reg); } 434 435 MiscReg readMiscReg(int misc_reg) 436 { return actualTC->readMiscReg(misc_reg); } 437 438 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 439 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 440 --- 80 unchanged lines hidden --- |