1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include <iostream> 35#include <string> 36 37#include "arch/registers.hh" 38#include "arch/types.hh" 39#include "base/types.hh" 40#include "config/full_system.hh" 41#include "config/the_isa.hh" 42 43// @todo: Figure out a more architecture independent way to obtain the ITB and 44// DTB pointers. 45namespace TheISA 46{ 47 class TLB; 48} 49class BaseCPU; 50class Checkpoint; 51class Decoder; 52class EndQuiesceEvent; 53class TranslatingPort; 54class FunctionalPort; 55class VirtualPort; 56class Process; 57class System; 58namespace TheISA { 59 namespace Kernel { 60 class Statistics; 61 }; 62}; 63 64/** 65 * ThreadContext is the external interface to all thread state for 66 * anything outside of the CPU. It provides all accessor methods to 67 * state that might be needed by external objects, ranging from 68 * register values to things such as kernel stats. It is an abstract 69 * base class; the CPU can create its own ThreadContext by either 70 * deriving from it, or using the templated ProxyThreadContext. 71 * 72 * The ThreadContext is slightly different than the ExecContext. The 73 * ThreadContext provides access to an individual thread's state; an 74 * ExecContext provides ISA access to the CPU (meaning it is 75 * implicitly multithreaded on SMT systems). Additionally the 76 * ThreadState is an abstract class that exactly defines the 77 * interface; the ExecContext is a more implicit interface that must 78 * be implemented so that the ISA can access whatever state it needs. 79 */ 80class ThreadContext 81{ 82 protected: 83 typedef TheISA::MachInst MachInst; 84 typedef TheISA::IntReg IntReg; 85 typedef TheISA::FloatReg FloatReg; 86 typedef TheISA::FloatRegBits FloatRegBits; 87 typedef TheISA::MiscReg MiscReg; 88 public: 89 90 enum Status 91 { 92 /// Running. Instructions should be executed only when 93 /// the context is in this state. 94 Active, 95 96 /// Temporarily inactive. Entered while waiting for 97 /// synchronization, etc. 98 Suspended, 99 100 /// Permanently shut down. Entered when target executes 101 /// m5exit pseudo-instruction. When all contexts enter 102 /// this state, the simulation will terminate. 103 Halted 104 }; 105 106 virtual ~ThreadContext() { }; 107 108 virtual BaseCPU *getCpuPtr() = 0; 109 110 virtual int cpuId() = 0; 111 112 virtual int threadId() = 0; 113 114 virtual void setThreadId(int id) = 0; 115 116 virtual int contextId() = 0; 117 118 virtual void setContextId(int id) = 0; 119 120 virtual TheISA::TLB *getITBPtr() = 0; 121 122 virtual TheISA::TLB *getDTBPtr() = 0; 123 124 virtual Decoder *getDecoderPtr() = 0; 125 126 virtual System *getSystemPtr() = 0; 127 128#if FULL_SYSTEM 129 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 130 131 virtual void connectMemPorts(ThreadContext *tc) = 0;
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132#else
133 virtual Process *getProcessPtr() = 0;
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132#endif
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133 virtual Process *getProcessPtr() = 0; |
134 135 virtual TranslatingPort *getMemPort() = 0; 136 137 virtual VirtualPort *getVirtPort() = 0; 138 139 virtual FunctionalPort *getPhysPort() = 0; 140 141 virtual Status status() const = 0; 142 143 virtual void setStatus(Status new_status) = 0; 144 145 /// Set the status to Active. Optional delay indicates number of 146 /// cycles to wait before beginning execution. 147 virtual void activate(int delay = 1) = 0; 148 149 /// Set the status to Suspended. 150 virtual void suspend(int delay = 0) = 0; 151 152 /// Set the status to Halted. 153 virtual void halt(int delay = 0) = 0; 154 155#if FULL_SYSTEM 156 virtual void dumpFuncProfile() = 0; 157#endif 158 159 virtual void takeOverFrom(ThreadContext *old_context) = 0; 160 161 virtual void regStats(const std::string &name) = 0; 162 163 virtual void serialize(std::ostream &os) = 0; 164 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 165 166#if FULL_SYSTEM 167 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 168 169 // Not necessarily the best location for these... 170 // Having an extra function just to read these is obnoxious 171 virtual Tick readLastActivate() = 0; 172 virtual Tick readLastSuspend() = 0; 173 174 virtual void profileClear() = 0; 175 virtual void profileSample() = 0; 176#endif 177 178 virtual void copyArchRegs(ThreadContext *tc) = 0; 179 180 virtual void clearArchRegs() = 0; 181 182 // 183 // New accessors for new decoder. 184 // 185 virtual uint64_t readIntReg(int reg_idx) = 0; 186 187 virtual FloatReg readFloatReg(int reg_idx) = 0; 188 189 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 190 191 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 192 193 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 194 195 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 196 197 virtual TheISA::PCState pcState() = 0; 198 199 virtual void pcState(const TheISA::PCState &val) = 0; 200 201 virtual Addr instAddr() = 0; 202 203 virtual Addr nextInstAddr() = 0; 204 205 virtual MicroPC microPC() = 0; 206 207 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 208 209 virtual MiscReg readMiscReg(int misc_reg) = 0; 210 211 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 212 213 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 214 215 virtual int flattenIntIndex(int reg) = 0; 216 virtual int flattenFloatIndex(int reg) = 0; 217 218 virtual uint64_t 219 readRegOtherThread(int misc_reg, ThreadID tid) 220 { 221 return 0; 222 } 223 224 virtual void 225 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 226 { 227 } 228 229 // Also not necessarily the best location for these two. Hopefully will go 230 // away once we decide upon where st cond failures goes. 231 virtual unsigned readStCondFailures() = 0; 232 233 virtual void setStCondFailures(unsigned sc_failures) = 0; 234 235 // Only really makes sense for old CPU model. Still could be useful though. 236 virtual bool misspeculating() = 0; 237 238#if !FULL_SYSTEM 239 // Same with st cond failures. 240 virtual Counter readFuncExeInst() = 0; 241 242 virtual void syscall(int64_t callnum) = 0; 243 244 // This function exits the thread context in the CPU and returns 245 // 1 if the CPU has no more active threads (meaning it's OK to exit); 246 // Used in syscall-emulation mode when a thread calls the exit syscall. 247 virtual int exit() { return 1; }; 248#endif 249 250 /** function to compare two thread contexts (for debugging) */ 251 static void compare(ThreadContext *one, ThreadContext *two); 252}; 253 254/** 255 * ProxyThreadContext class that provides a way to implement a 256 * ThreadContext without having to derive from it. ThreadContext is an 257 * abstract class, so anything that derives from it and uses its 258 * interface will pay the overhead of virtual function calls. This 259 * class is created to enable a user-defined Thread object to be used 260 * wherever ThreadContexts are used, without paying the overhead of 261 * virtual function calls when it is used by itself. See 262 * simple_thread.hh for an example of this. 263 */ 264template <class TC> 265class ProxyThreadContext : public ThreadContext 266{ 267 public: 268 ProxyThreadContext(TC *actual_tc) 269 { actualTC = actual_tc; } 270 271 private: 272 TC *actualTC; 273 274 public: 275 276 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 277 278 int cpuId() { return actualTC->cpuId(); } 279 280 int threadId() { return actualTC->threadId(); } 281 282 void setThreadId(int id) { return actualTC->setThreadId(id); } 283 284 int contextId() { return actualTC->contextId(); } 285 286 void setContextId(int id) { actualTC->setContextId(id); } 287 288 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 289 290 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 291 292 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 293 294 System *getSystemPtr() { return actualTC->getSystemPtr(); } 295 296#if FULL_SYSTEM 297 TheISA::Kernel::Statistics *getKernelStats() 298 { return actualTC->getKernelStats(); } 299 300 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
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302#else
303 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
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301#endif
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302 Process *getProcessPtr() { return actualTC->getProcessPtr(); } |
303 304 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 305 306 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 307 308 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 309 310 Status status() const { return actualTC->status(); } 311 312 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 313 314 /// Set the status to Active. Optional delay indicates number of 315 /// cycles to wait before beginning execution. 316 void activate(int delay = 1) { actualTC->activate(delay); } 317 318 /// Set the status to Suspended. 319 void suspend(int delay = 0) { actualTC->suspend(); } 320 321 /// Set the status to Halted. 322 void halt(int delay = 0) { actualTC->halt(); } 323 324#if FULL_SYSTEM 325 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 326#endif 327 328 void takeOverFrom(ThreadContext *oldContext) 329 { actualTC->takeOverFrom(oldContext); } 330 331 void regStats(const std::string &name) { actualTC->regStats(name); } 332 333 void serialize(std::ostream &os) { actualTC->serialize(os); } 334 void unserialize(Checkpoint *cp, const std::string §ion) 335 { actualTC->unserialize(cp, section); } 336 337#if FULL_SYSTEM 338 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 339 340 Tick readLastActivate() { return actualTC->readLastActivate(); } 341 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 342 343 void profileClear() { return actualTC->profileClear(); } 344 void profileSample() { return actualTC->profileSample(); } 345#endif 346 347 // @todo: Do I need this? 348 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 349 350 void clearArchRegs() { actualTC->clearArchRegs(); } 351 352 // 353 // New accessors for new decoder. 354 // 355 uint64_t readIntReg(int reg_idx) 356 { return actualTC->readIntReg(reg_idx); } 357 358 FloatReg readFloatReg(int reg_idx) 359 { return actualTC->readFloatReg(reg_idx); } 360 361 FloatRegBits readFloatRegBits(int reg_idx) 362 { return actualTC->readFloatRegBits(reg_idx); } 363 364 void setIntReg(int reg_idx, uint64_t val) 365 { actualTC->setIntReg(reg_idx, val); } 366 367 void setFloatReg(int reg_idx, FloatReg val) 368 { actualTC->setFloatReg(reg_idx, val); } 369 370 void setFloatRegBits(int reg_idx, FloatRegBits val) 371 { actualTC->setFloatRegBits(reg_idx, val); } 372 373 TheISA::PCState pcState() { return actualTC->pcState(); } 374 375 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 376 377 Addr instAddr() { return actualTC->instAddr(); } 378 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 379 MicroPC microPC() { return actualTC->microPC(); } 380 381 bool readPredicate() { return actualTC->readPredicate(); } 382 383 void setPredicate(bool val) 384 { actualTC->setPredicate(val); } 385 386 MiscReg readMiscRegNoEffect(int misc_reg) 387 { return actualTC->readMiscRegNoEffect(misc_reg); } 388 389 MiscReg readMiscReg(int misc_reg) 390 { return actualTC->readMiscReg(misc_reg); } 391 392 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 393 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 394 395 void setMiscReg(int misc_reg, const MiscReg &val) 396 { return actualTC->setMiscReg(misc_reg, val); } 397 398 int flattenIntIndex(int reg) 399 { return actualTC->flattenIntIndex(reg); } 400 401 int flattenFloatIndex(int reg) 402 { return actualTC->flattenFloatIndex(reg); } 403 404 unsigned readStCondFailures() 405 { return actualTC->readStCondFailures(); } 406 407 void setStCondFailures(unsigned sc_failures) 408 { actualTC->setStCondFailures(sc_failures); } 409 410 // @todo: Fix this! 411 bool misspeculating() { return actualTC->misspeculating(); } 412 413#if !FULL_SYSTEM 414 void syscall(int64_t callnum) 415 { actualTC->syscall(callnum); } 416 417 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 418#endif 419}; 420 421#endif
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