1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_THREAD_CONTEXT_HH__ 45#define __CPU_THREAD_CONTEXT_HH__ 46 47#include <iostream> 48#include <string> 49 50#include "arch/registers.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/the_isa.hh" 54#include "cpu/reg_class.hh" 55 56// @todo: Figure out a more architecture independent way to obtain the ITB and 57// DTB pointers. 58namespace TheISA 59{ 60 class ISA; 61 class Decoder; 62} 63class BaseCPU; 64class BaseTLB; 65class CheckerCPU; 66class Checkpoint; 67class EndQuiesceEvent; 68class SETranslatingPortProxy; 69class FSTranslatingPortProxy; 70class PortProxy; 71class Process; 72class System; 73namespace TheISA { 74 namespace Kernel { 75 class Statistics; 76 } 77} 78 79/** 80 * ThreadContext is the external interface to all thread state for 81 * anything outside of the CPU. It provides all accessor methods to 82 * state that might be needed by external objects, ranging from 83 * register values to things such as kernel stats. It is an abstract 84 * base class; the CPU can create its own ThreadContext by 85 * deriving from it. 86 * 87 * The ThreadContext is slightly different than the ExecContext. The 88 * ThreadContext provides access to an individual thread's state; an 89 * ExecContext provides ISA access to the CPU (meaning it is 90 * implicitly multithreaded on SMT systems). Additionally the 91 * ThreadState is an abstract class that exactly defines the 92 * interface; the ExecContext is a more implicit interface that must 93 * be implemented so that the ISA can access whatever state it needs. 94 */ 95class ThreadContext 96{ 97 protected: 98 typedef TheISA::MachInst MachInst; 99 using VecRegContainer = TheISA::VecRegContainer; 100 using VecElem = TheISA::VecElem; 101 using VecPredRegContainer = TheISA::VecPredRegContainer; 102 103 public: 104 105 enum Status 106 { 107 /// Running. Instructions should be executed only when 108 /// the context is in this state. 109 Active, 110 111 /// Temporarily inactive. Entered while waiting for 112 /// synchronization, etc. 113 Suspended, 114 115 /// Trying to exit and waiting for an event to completely exit. 116 /// Entered when target executes an exit syscall. 117 Halting, 118 119 /// Permanently shut down. Entered when target executes 120 /// m5exit pseudo-instruction. When all contexts enter 121 /// this state, the simulation will terminate. 122 Halted 123 }; 124 125 virtual ~ThreadContext() { }; 126 127 virtual BaseCPU *getCpuPtr() = 0; 128 129 virtual int cpuId() const = 0; 130 131 virtual uint32_t socketId() const = 0; 132 133 virtual int threadId() const = 0; 134 135 virtual void setThreadId(int id) = 0; 136 137 virtual ContextID contextId() const = 0; 138 139 virtual void setContextId(ContextID id) = 0; 140 141 virtual BaseTLB *getITBPtr() = 0; 142 143 virtual BaseTLB *getDTBPtr() = 0; 144 145 virtual CheckerCPU *getCheckerCpuPtr() = 0; 146 147 virtual TheISA::ISA *getIsaPtr() = 0; 148 149 virtual TheISA::Decoder *getDecoderPtr() = 0; 150 151 virtual System *getSystemPtr() = 0; 152 153 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 154 155 virtual PortProxy &getPhysProxy() = 0; 156 157 virtual FSTranslatingPortProxy &getVirtProxy() = 0; 158 159 /** 160 * Initialise the physical and virtual port proxies and tie them to 161 * the data port of the CPU. 162 * 163 * tc ThreadContext for the virtual-to-physical translation 164 */ 165 virtual void initMemProxies(ThreadContext *tc) = 0; 166 167 virtual SETranslatingPortProxy &getMemProxy() = 0; 168 169 virtual Process *getProcessPtr() = 0; 170 171 virtual void setProcessPtr(Process *p) = 0; 172 173 virtual Status status() const = 0; 174 175 virtual void setStatus(Status new_status) = 0; 176 177 /// Set the status to Active. 178 virtual void activate() = 0; 179 180 /// Set the status to Suspended. 181 virtual void suspend() = 0; 182 183 /// Set the status to Halted. 184 virtual void halt() = 0; 185 186 /// Quiesce thread context 187 void quiesce(); 188 189 /// Quiesce, suspend, and schedule activate at resume 190 void quiesceTick(Tick resume); 191 192 virtual void dumpFuncProfile() = 0; 193 194 virtual void takeOverFrom(ThreadContext *old_context) = 0; 195 196 virtual void regStats(const std::string &name) = 0; 197 198 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 199 200 // Not necessarily the best location for these... 201 // Having an extra function just to read these is obnoxious 202 virtual Tick readLastActivate() = 0; 203 virtual Tick readLastSuspend() = 0; 204 205 virtual void profileClear() = 0; 206 virtual void profileSample() = 0; 207 208 virtual void copyArchRegs(ThreadContext *tc) = 0; 209 210 virtual void clearArchRegs() = 0; 211 212 // 213 // New accessors for new decoder. 214 // 215 virtual RegVal readIntReg(RegIndex reg_idx) const = 0; 216 217 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0; 218 219 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 220 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 221 222 /** Vector Register Lane Interfaces. */ 223 /** @{ */ 224 /** Reads source vector 8bit operand. */ 225 virtual ConstVecLane8 226 readVec8BitLaneReg(const RegId& reg) const = 0; 227 228 /** Reads source vector 16bit operand. */ 229 virtual ConstVecLane16 230 readVec16BitLaneReg(const RegId& reg) const = 0; 231 232 /** Reads source vector 32bit operand. */ 233 virtual ConstVecLane32 234 readVec32BitLaneReg(const RegId& reg) const = 0; 235 236 /** Reads source vector 64bit operand. */ 237 virtual ConstVecLane64 238 readVec64BitLaneReg(const RegId& reg) const = 0; 239 240 /** Write a lane of the destination vector register. */ 241 virtual void setVecLane(const RegId& reg, 242 const LaneData<LaneSize::Byte>& val) = 0; 243 virtual void setVecLane(const RegId& reg, 244 const LaneData<LaneSize::TwoByte>& val) = 0; 245 virtual void setVecLane(const RegId& reg, 246 const LaneData<LaneSize::FourByte>& val) = 0; 247 virtual void setVecLane(const RegId& reg, 248 const LaneData<LaneSize::EightByte>& val) = 0; 249 /** @} */ 250 251 virtual const VecElem& readVecElem(const RegId& reg) const = 0; 252 253 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg) 254 const = 0; 255 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0; 256 257 virtual RegVal readCCReg(RegIndex reg_idx) const = 0; 258 259 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0; 260 261 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0; 262 263 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 264 265 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 266 267 virtual void setVecPredReg(const RegId& reg, 268 const VecPredRegContainer& val) = 0; 269 270 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0; 271 272 virtual TheISA::PCState pcState() const = 0; 273 274 virtual void pcState(const TheISA::PCState &val) = 0; 275 276 void 277 setNPC(Addr val) 278 { 279 TheISA::PCState pc_state = pcState(); 280 pc_state.setNPC(val); 281 pcState(pc_state); 282 } 283 284 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 285 286 virtual Addr instAddr() const = 0; 287 288 virtual Addr nextInstAddr() const = 0; 289 290 virtual MicroPC microPC() const = 0; 291 292 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; 293 294 virtual RegVal readMiscReg(RegIndex misc_reg) = 0; 295 296 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0; 297 298 virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0; 299 300 virtual RegId flattenRegId(const RegId& regId) const = 0; 301 |
302 // Also not necessarily the best location for these two. Hopefully will go 303 // away once we decide upon where st cond failures goes. 304 virtual unsigned readStCondFailures() const = 0; 305 306 virtual void setStCondFailures(unsigned sc_failures) = 0; 307 308 // Same with st cond failures. 309 virtual Counter readFuncExeInst() const = 0; 310 311 virtual void syscall(int64_t callnum, Fault *fault) = 0; 312 313 // This function exits the thread context in the CPU and returns 314 // 1 if the CPU has no more active threads (meaning it's OK to exit); 315 // Used in syscall-emulation mode when a thread calls the exit syscall. 316 virtual int exit() { return 1; }; 317 318 /** function to compare two thread contexts (for debugging) */ 319 static void compare(ThreadContext *one, ThreadContext *two); 320 321 /** @{ */ 322 /** 323 * Flat register interfaces 324 * 325 * Some architectures have different registers visible in 326 * different modes. Such architectures "flatten" a register (see 327 * flattenRegId()) to map it into the 328 * gem5 register file. This interface provides a flat interface to 329 * the underlying register file, which allows for example 330 * serialization code to access all registers. 331 */ 332 333 virtual RegVal readIntRegFlat(RegIndex idx) const = 0; 334 virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0; 335 336 virtual RegVal readFloatRegFlat(RegIndex idx) const = 0; 337 virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0; 338 339 virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0; 340 virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0; 341 virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0; 342 343 virtual const VecElem& readVecElemFlat(RegIndex idx, 344 const ElemIndex& elemIdx) const = 0; 345 virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, 346 const VecElem& val) = 0; 347 348 virtual const VecPredRegContainer & 349 readVecPredRegFlat(RegIndex idx) const = 0; 350 virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0; 351 virtual void setVecPredRegFlat(RegIndex idx, 352 const VecPredRegContainer& val) = 0; 353 354 virtual RegVal readCCRegFlat(RegIndex idx) const = 0; 355 virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0; 356 /** @} */ 357 358}; 359 360/** @{ */ 361/** 362 * Thread context serialization helpers 363 * 364 * These helper functions provide a way to the data in a 365 * ThreadContext. They are provided as separate helper function since 366 * implementing them as members of the ThreadContext interface would 367 * be confusing when the ThreadContext is exported via a proxy. 368 */ 369 370void serialize(const ThreadContext &tc, CheckpointOut &cp); 371void unserialize(ThreadContext &tc, CheckpointIn &cp); 372 373/** @} */ 374 375 376/** 377 * Copy state between thread contexts in preparation for CPU handover. 378 * 379 * @note This method modifies the old thread contexts as well as the 380 * new thread context. The old thread context will have its quiesce 381 * event descheduled if it is scheduled and its status set to halted. 382 * 383 * @param new_tc Destination ThreadContext. 384 * @param old_tc Source ThreadContext. 385 */ 386void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 387 388#endif |