1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 101 unchanged lines hidden (view full) --- 110 /// this state, the simulation will terminate. 111 Halted 112 }; 113 114 virtual ~ThreadContext() { }; 115 116 virtual BaseCPU *getCpuPtr() = 0; 117 |
118 virtual int cpuId() = 0; |
119 |
120 virtual TheISA::ITB *getITBPtr() = 0; 121 122 virtual TheISA::DTB *getDTBPtr() = 0; 123 124#if FULL_SYSTEM 125 virtual System *getSystemPtr() = 0; 126 127 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; --- 165 unchanged lines hidden (view full) --- 293 294 private: 295 TC *actualTC; 296 297 public: 298 299 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 300 |
301 int cpuId() { return actualTC->cpuId(); } |
302 |
303 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 304 305 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 306 307#if FULL_SYSTEM 308 System *getSystemPtr() { return actualTC->getSystemPtr(); } 309 310 TheISA::Kernel::Statistics *getKernelStats() --- 155 unchanged lines hidden --- |