1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 220 unchanged lines hidden (view full) --- 229 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 230 231 virtual MiscReg readMiscReg(int misc_reg) = 0; 232 233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 234 235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 236 |
237 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } 238 239 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; 240 |
241 // Also not necessarily the best location for these two. Hopefully will go 242 // away once we decide upon where st cond failures goes. 243 virtual unsigned readStCondFailures() = 0; 244 245 virtual void setStCondFailures(unsigned sc_failures) = 0; 246 247 // Only really makes sense for old CPU model. Still could be useful though. 248 virtual bool misspeculating() = 0; --- 215 unchanged lines hidden --- |