1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 222 unchanged lines hidden (view full) --- 231 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 232 233 // Also not necessarily the best location for these two. Hopefully will go 234 // away once we decide upon where st cond failures goes. 235 virtual unsigned readStCondFailures() = 0; 236 237 virtual void setStCondFailures(unsigned sc_failures) = 0; 238 |
239 // Only really makes sense for old CPU model. Still could be useful though. 240 virtual bool misspeculating() = 0; 241 242#if !FULL_SYSTEM 243 virtual IntReg getSyscallArg(int i) = 0; 244 245 // used to shift args for indirect syscall 246 virtual void setSyscallArg(int i, IntReg val) = 0; --- 168 unchanged lines hidden (view full) --- 415 void setMiscRegWithEffect(int misc_reg, const MiscReg &val) 416 { return actualTC->setMiscRegWithEffect(misc_reg, val); } 417 418 unsigned readStCondFailures() 419 { return actualTC->readStCondFailures(); } 420 421 void setStCondFailures(unsigned sc_failures) 422 { actualTC->setStCondFailures(sc_failures); } |
423 424 // @todo: Fix this! 425 bool misspeculating() { return actualTC->misspeculating(); } 426 427#if !FULL_SYSTEM 428 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 429 430 // used to shift args for indirect syscall --- 17 unchanged lines hidden --- |