1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 37 unchanged lines hidden (view full) --- 46 47#include <iostream> 48#include <string> 49 50#include "arch/registers.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/the_isa.hh" |
54#include "cpu/reg_class.hh" |
55 56// @todo: Figure out a more architecture independent way to obtain the ITB and 57// DTB pointers. 58namespace TheISA 59{ 60 class Decoder; 61 class TLB; 62} --- 188 unchanged lines hidden (view full) --- 251 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 252 253 virtual int flattenIntIndex(int reg) = 0; 254 virtual int flattenFloatIndex(int reg) = 0; 255 virtual int flattenCCIndex(int reg) = 0; 256 virtual int flattenMiscIndex(int reg) = 0; 257 258 virtual uint64_t |
259 readRegOtherThread(RegId misc_reg, ThreadID tid) |
260 { 261 return 0; 262 } 263 264 virtual void |
265 setRegOtherThread(RegId misc_reg, const MiscReg &val, ThreadID tid) |
266 { 267 } 268 269 // Also not necessarily the best location for these two. Hopefully will go 270 // away once we decide upon where st cond failures goes. 271 virtual unsigned readStCondFailures() = 0; 272 273 virtual void setStCondFailures(unsigned sc_failures) = 0; --- 272 unchanged lines hidden --- |