1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_THREAD_CONTEXT_HH__
44#define __CPU_THREAD_CONTEXT_HH__
45
46#include <iostream>
47#include <string>
48
49#include "arch/registers.hh"
50#include "arch/types.hh"
51#include "base/types.hh"
52#include "config/the_isa.hh"
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_THREAD_CONTEXT_HH__
44#define __CPU_THREAD_CONTEXT_HH__
45
46#include <iostream>
47#include <string>
48
49#include "arch/registers.hh"
50#include "arch/types.hh"
51#include "base/types.hh"
52#include "config/the_isa.hh"
|
53#include "config/use_checker.hh"
| |
54
55// @todo: Figure out a more architecture independent way to obtain the ITB and
56// DTB pointers.
57namespace TheISA
58{
59 class TLB;
60}
61class BaseCPU;
| 53
54// @todo: Figure out a more architecture independent way to obtain the ITB and
55// DTB pointers.
56namespace TheISA
57{
58 class TLB;
59}
60class BaseCPU;
|
| 61class CheckerCPU;
|
62class Checkpoint;
63class Decoder;
64class EndQuiesceEvent;
65class SETranslatingPortProxy;
66class FSTranslatingPortProxy;
67class PortProxy;
68class Process;
69class System;
70namespace TheISA {
71 namespace Kernel {
72 class Statistics;
73 };
74};
75
76/**
77 * ThreadContext is the external interface to all thread state for
78 * anything outside of the CPU. It provides all accessor methods to
79 * state that might be needed by external objects, ranging from
80 * register values to things such as kernel stats. It is an abstract
81 * base class; the CPU can create its own ThreadContext by either
82 * deriving from it, or using the templated ProxyThreadContext.
83 *
84 * The ThreadContext is slightly different than the ExecContext. The
85 * ThreadContext provides access to an individual thread's state; an
86 * ExecContext provides ISA access to the CPU (meaning it is
87 * implicitly multithreaded on SMT systems). Additionally the
88 * ThreadState is an abstract class that exactly defines the
89 * interface; the ExecContext is a more implicit interface that must
90 * be implemented so that the ISA can access whatever state it needs.
91 */
92class ThreadContext
93{
94 protected:
95 typedef TheISA::MachInst MachInst;
96 typedef TheISA::IntReg IntReg;
97 typedef TheISA::FloatReg FloatReg;
98 typedef TheISA::FloatRegBits FloatRegBits;
99 typedef TheISA::MiscReg MiscReg;
100 public:
101
102 enum Status
103 {
104 /// Running. Instructions should be executed only when
105 /// the context is in this state.
106 Active,
107
108 /// Temporarily inactive. Entered while waiting for
109 /// synchronization, etc.
110 Suspended,
111
112 /// Permanently shut down. Entered when target executes
113 /// m5exit pseudo-instruction. When all contexts enter
114 /// this state, the simulation will terminate.
115 Halted
116 };
117
118 virtual ~ThreadContext() { };
119
120 virtual BaseCPU *getCpuPtr() = 0;
121
122 virtual int cpuId() = 0;
123
124 virtual int threadId() = 0;
125
126 virtual void setThreadId(int id) = 0;
127
128 virtual int contextId() = 0;
129
130 virtual void setContextId(int id) = 0;
131
132 virtual TheISA::TLB *getITBPtr() = 0;
133
134 virtual TheISA::TLB *getDTBPtr() = 0;
135
| 62class Checkpoint;
63class Decoder;
64class EndQuiesceEvent;
65class SETranslatingPortProxy;
66class FSTranslatingPortProxy;
67class PortProxy;
68class Process;
69class System;
70namespace TheISA {
71 namespace Kernel {
72 class Statistics;
73 };
74};
75
76/**
77 * ThreadContext is the external interface to all thread state for
78 * anything outside of the CPU. It provides all accessor methods to
79 * state that might be needed by external objects, ranging from
80 * register values to things such as kernel stats. It is an abstract
81 * base class; the CPU can create its own ThreadContext by either
82 * deriving from it, or using the templated ProxyThreadContext.
83 *
84 * The ThreadContext is slightly different than the ExecContext. The
85 * ThreadContext provides access to an individual thread's state; an
86 * ExecContext provides ISA access to the CPU (meaning it is
87 * implicitly multithreaded on SMT systems). Additionally the
88 * ThreadState is an abstract class that exactly defines the
89 * interface; the ExecContext is a more implicit interface that must
90 * be implemented so that the ISA can access whatever state it needs.
91 */
92class ThreadContext
93{
94 protected:
95 typedef TheISA::MachInst MachInst;
96 typedef TheISA::IntReg IntReg;
97 typedef TheISA::FloatReg FloatReg;
98 typedef TheISA::FloatRegBits FloatRegBits;
99 typedef TheISA::MiscReg MiscReg;
100 public:
101
102 enum Status
103 {
104 /// Running. Instructions should be executed only when
105 /// the context is in this state.
106 Active,
107
108 /// Temporarily inactive. Entered while waiting for
109 /// synchronization, etc.
110 Suspended,
111
112 /// Permanently shut down. Entered when target executes
113 /// m5exit pseudo-instruction. When all contexts enter
114 /// this state, the simulation will terminate.
115 Halted
116 };
117
118 virtual ~ThreadContext() { };
119
120 virtual BaseCPU *getCpuPtr() = 0;
121
122 virtual int cpuId() = 0;
123
124 virtual int threadId() = 0;
125
126 virtual void setThreadId(int id) = 0;
127
128 virtual int contextId() = 0;
129
130 virtual void setContextId(int id) = 0;
131
132 virtual TheISA::TLB *getITBPtr() = 0;
133
134 virtual TheISA::TLB *getDTBPtr() = 0;
135
|
136#if USE_CHECKER
137 virtual BaseCPU *getCheckerCpuPtr() = 0;
138#endif
| 136 virtual CheckerCPU *getCheckerCpuPtr() = 0;
|
139
140 virtual Decoder *getDecoderPtr() = 0;
141
142 virtual System *getSystemPtr() = 0;
143
144 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
145
146 virtual PortProxy &getPhysProxy() = 0;
147
148 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
149
150 /**
151 * Initialise the physical and virtual port proxies and tie them to
152 * the data port of the CPU.
153 *
154 * tc ThreadContext for the virtual-to-physical translation
155 */
156 virtual void initMemProxies(ThreadContext *tc) = 0;
157
158 virtual SETranslatingPortProxy &getMemProxy() = 0;
159
160 virtual Process *getProcessPtr() = 0;
161
162 virtual Status status() const = 0;
163
164 virtual void setStatus(Status new_status) = 0;
165
166 /// Set the status to Active. Optional delay indicates number of
167 /// cycles to wait before beginning execution.
168 virtual void activate(int delay = 1) = 0;
169
170 /// Set the status to Suspended.
171 virtual void suspend(int delay = 0) = 0;
172
173 /// Set the status to Halted.
174 virtual void halt(int delay = 0) = 0;
175
176 virtual void dumpFuncProfile() = 0;
177
178 virtual void takeOverFrom(ThreadContext *old_context) = 0;
179
180 virtual void regStats(const std::string &name) = 0;
181
182 virtual void serialize(std::ostream &os) = 0;
183 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
184
185 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
186
187 // Not necessarily the best location for these...
188 // Having an extra function just to read these is obnoxious
189 virtual Tick readLastActivate() = 0;
190 virtual Tick readLastSuspend() = 0;
191
192 virtual void profileClear() = 0;
193 virtual void profileSample() = 0;
194
195 virtual void copyArchRegs(ThreadContext *tc) = 0;
196
197 virtual void clearArchRegs() = 0;
198
199 //
200 // New accessors for new decoder.
201 //
202 virtual uint64_t readIntReg(int reg_idx) = 0;
203
204 virtual FloatReg readFloatReg(int reg_idx) = 0;
205
206 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
207
208 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
209
210 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
211
212 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
213
214 virtual TheISA::PCState pcState() = 0;
215
216 virtual void pcState(const TheISA::PCState &val) = 0;
217
| 137
138 virtual Decoder *getDecoderPtr() = 0;
139
140 virtual System *getSystemPtr() = 0;
141
142 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
143
144 virtual PortProxy &getPhysProxy() = 0;
145
146 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
147
148 /**
149 * Initialise the physical and virtual port proxies and tie them to
150 * the data port of the CPU.
151 *
152 * tc ThreadContext for the virtual-to-physical translation
153 */
154 virtual void initMemProxies(ThreadContext *tc) = 0;
155
156 virtual SETranslatingPortProxy &getMemProxy() = 0;
157
158 virtual Process *getProcessPtr() = 0;
159
160 virtual Status status() const = 0;
161
162 virtual void setStatus(Status new_status) = 0;
163
164 /// Set the status to Active. Optional delay indicates number of
165 /// cycles to wait before beginning execution.
166 virtual void activate(int delay = 1) = 0;
167
168 /// Set the status to Suspended.
169 virtual void suspend(int delay = 0) = 0;
170
171 /// Set the status to Halted.
172 virtual void halt(int delay = 0) = 0;
173
174 virtual void dumpFuncProfile() = 0;
175
176 virtual void takeOverFrom(ThreadContext *old_context) = 0;
177
178 virtual void regStats(const std::string &name) = 0;
179
180 virtual void serialize(std::ostream &os) = 0;
181 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
182
183 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
184
185 // Not necessarily the best location for these...
186 // Having an extra function just to read these is obnoxious
187 virtual Tick readLastActivate() = 0;
188 virtual Tick readLastSuspend() = 0;
189
190 virtual void profileClear() = 0;
191 virtual void profileSample() = 0;
192
193 virtual void copyArchRegs(ThreadContext *tc) = 0;
194
195 virtual void clearArchRegs() = 0;
196
197 //
198 // New accessors for new decoder.
199 //
200 virtual uint64_t readIntReg(int reg_idx) = 0;
201
202 virtual FloatReg readFloatReg(int reg_idx) = 0;
203
204 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
205
206 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
207
208 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
209
210 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
211
212 virtual TheISA::PCState pcState() = 0;
213
214 virtual void pcState(const TheISA::PCState &val) = 0;
215
|
218#if USE_CHECKER
| |
219 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
| 216 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
|
220#endif
| |
221
222 virtual Addr instAddr() = 0;
223
224 virtual Addr nextInstAddr() = 0;
225
226 virtual MicroPC microPC() = 0;
227
228 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
229
230 virtual MiscReg readMiscReg(int misc_reg) = 0;
231
232 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
233
234 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
235
236 virtual int flattenIntIndex(int reg) = 0;
237 virtual int flattenFloatIndex(int reg) = 0;
238
239 virtual uint64_t
240 readRegOtherThread(int misc_reg, ThreadID tid)
241 {
242 return 0;
243 }
244
245 virtual void
246 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
247 {
248 }
249
250 // Also not necessarily the best location for these two. Hopefully will go
251 // away once we decide upon where st cond failures goes.
252 virtual unsigned readStCondFailures() = 0;
253
254 virtual void setStCondFailures(unsigned sc_failures) = 0;
255
256 // Only really makes sense for old CPU model. Still could be useful though.
257 virtual bool misspeculating() = 0;
258
259 // Same with st cond failures.
260 virtual Counter readFuncExeInst() = 0;
261
262 virtual void syscall(int64_t callnum) = 0;
263
264 // This function exits the thread context in the CPU and returns
265 // 1 if the CPU has no more active threads (meaning it's OK to exit);
266 // Used in syscall-emulation mode when a thread calls the exit syscall.
267 virtual int exit() { return 1; };
268
269 /** function to compare two thread contexts (for debugging) */
270 static void compare(ThreadContext *one, ThreadContext *two);
271};
272
273/**
274 * ProxyThreadContext class that provides a way to implement a
275 * ThreadContext without having to derive from it. ThreadContext is an
276 * abstract class, so anything that derives from it and uses its
277 * interface will pay the overhead of virtual function calls. This
278 * class is created to enable a user-defined Thread object to be used
279 * wherever ThreadContexts are used, without paying the overhead of
280 * virtual function calls when it is used by itself. See
281 * simple_thread.hh for an example of this.
282 */
283template <class TC>
284class ProxyThreadContext : public ThreadContext
285{
286 public:
287 ProxyThreadContext(TC *actual_tc)
288 { actualTC = actual_tc; }
289
290 private:
291 TC *actualTC;
292
293 public:
294
295 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
296
297 int cpuId() { return actualTC->cpuId(); }
298
299 int threadId() { return actualTC->threadId(); }
300
301 void setThreadId(int id) { return actualTC->setThreadId(id); }
302
303 int contextId() { return actualTC->contextId(); }
304
305 void setContextId(int id) { actualTC->setContextId(id); }
306
307 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
308
309 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
310
| 217
218 virtual Addr instAddr() = 0;
219
220 virtual Addr nextInstAddr() = 0;
221
222 virtual MicroPC microPC() = 0;
223
224 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
225
226 virtual MiscReg readMiscReg(int misc_reg) = 0;
227
228 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
229
230 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
231
232 virtual int flattenIntIndex(int reg) = 0;
233 virtual int flattenFloatIndex(int reg) = 0;
234
235 virtual uint64_t
236 readRegOtherThread(int misc_reg, ThreadID tid)
237 {
238 return 0;
239 }
240
241 virtual void
242 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
243 {
244 }
245
246 // Also not necessarily the best location for these two. Hopefully will go
247 // away once we decide upon where st cond failures goes.
248 virtual unsigned readStCondFailures() = 0;
249
250 virtual void setStCondFailures(unsigned sc_failures) = 0;
251
252 // Only really makes sense for old CPU model. Still could be useful though.
253 virtual bool misspeculating() = 0;
254
255 // Same with st cond failures.
256 virtual Counter readFuncExeInst() = 0;
257
258 virtual void syscall(int64_t callnum) = 0;
259
260 // This function exits the thread context in the CPU and returns
261 // 1 if the CPU has no more active threads (meaning it's OK to exit);
262 // Used in syscall-emulation mode when a thread calls the exit syscall.
263 virtual int exit() { return 1; };
264
265 /** function to compare two thread contexts (for debugging) */
266 static void compare(ThreadContext *one, ThreadContext *two);
267};
268
269/**
270 * ProxyThreadContext class that provides a way to implement a
271 * ThreadContext without having to derive from it. ThreadContext is an
272 * abstract class, so anything that derives from it and uses its
273 * interface will pay the overhead of virtual function calls. This
274 * class is created to enable a user-defined Thread object to be used
275 * wherever ThreadContexts are used, without paying the overhead of
276 * virtual function calls when it is used by itself. See
277 * simple_thread.hh for an example of this.
278 */
279template <class TC>
280class ProxyThreadContext : public ThreadContext
281{
282 public:
283 ProxyThreadContext(TC *actual_tc)
284 { actualTC = actual_tc; }
285
286 private:
287 TC *actualTC;
288
289 public:
290
291 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
292
293 int cpuId() { return actualTC->cpuId(); }
294
295 int threadId() { return actualTC->threadId(); }
296
297 void setThreadId(int id) { return actualTC->setThreadId(id); }
298
299 int contextId() { return actualTC->contextId(); }
300
301 void setContextId(int id) { actualTC->setContextId(id); }
302
303 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
304
305 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
306
|
311#if USE_CHECKER
312 BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
313#endif
| 307 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
|
314
315 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
316
317 System *getSystemPtr() { return actualTC->getSystemPtr(); }
318
319 TheISA::Kernel::Statistics *getKernelStats()
320 { return actualTC->getKernelStats(); }
321
322 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
323
324 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
325
326 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
327
328 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
329
330 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
331
332 Status status() const { return actualTC->status(); }
333
334 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
335
336 /// Set the status to Active. Optional delay indicates number of
337 /// cycles to wait before beginning execution.
338 void activate(int delay = 1) { actualTC->activate(delay); }
339
340 /// Set the status to Suspended.
341 void suspend(int delay = 0) { actualTC->suspend(); }
342
343 /// Set the status to Halted.
344 void halt(int delay = 0) { actualTC->halt(); }
345
346 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
347
348 void takeOverFrom(ThreadContext *oldContext)
349 { actualTC->takeOverFrom(oldContext); }
350
351 void regStats(const std::string &name) { actualTC->regStats(name); }
352
353 void serialize(std::ostream &os) { actualTC->serialize(os); }
354 void unserialize(Checkpoint *cp, const std::string §ion)
355 { actualTC->unserialize(cp, section); }
356
357 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
358
359 Tick readLastActivate() { return actualTC->readLastActivate(); }
360 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
361
362 void profileClear() { return actualTC->profileClear(); }
363 void profileSample() { return actualTC->profileSample(); }
364
365 // @todo: Do I need this?
366 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
367
368 void clearArchRegs() { actualTC->clearArchRegs(); }
369
370 //
371 // New accessors for new decoder.
372 //
373 uint64_t readIntReg(int reg_idx)
374 { return actualTC->readIntReg(reg_idx); }
375
376 FloatReg readFloatReg(int reg_idx)
377 { return actualTC->readFloatReg(reg_idx); }
378
379 FloatRegBits readFloatRegBits(int reg_idx)
380 { return actualTC->readFloatRegBits(reg_idx); }
381
382 void setIntReg(int reg_idx, uint64_t val)
383 { actualTC->setIntReg(reg_idx, val); }
384
385 void setFloatReg(int reg_idx, FloatReg val)
386 { actualTC->setFloatReg(reg_idx, val); }
387
388 void setFloatRegBits(int reg_idx, FloatRegBits val)
389 { actualTC->setFloatRegBits(reg_idx, val); }
390
391 TheISA::PCState pcState() { return actualTC->pcState(); }
392
393 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
394
| 308
309 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
310
311 System *getSystemPtr() { return actualTC->getSystemPtr(); }
312
313 TheISA::Kernel::Statistics *getKernelStats()
314 { return actualTC->getKernelStats(); }
315
316 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
317
318 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
319
320 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
321
322 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
323
324 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
325
326 Status status() const { return actualTC->status(); }
327
328 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
329
330 /// Set the status to Active. Optional delay indicates number of
331 /// cycles to wait before beginning execution.
332 void activate(int delay = 1) { actualTC->activate(delay); }
333
334 /// Set the status to Suspended.
335 void suspend(int delay = 0) { actualTC->suspend(); }
336
337 /// Set the status to Halted.
338 void halt(int delay = 0) { actualTC->halt(); }
339
340 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
341
342 void takeOverFrom(ThreadContext *oldContext)
343 { actualTC->takeOverFrom(oldContext); }
344
345 void regStats(const std::string &name) { actualTC->regStats(name); }
346
347 void serialize(std::ostream &os) { actualTC->serialize(os); }
348 void unserialize(Checkpoint *cp, const std::string §ion)
349 { actualTC->unserialize(cp, section); }
350
351 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
352
353 Tick readLastActivate() { return actualTC->readLastActivate(); }
354 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
355
356 void profileClear() { return actualTC->profileClear(); }
357 void profileSample() { return actualTC->profileSample(); }
358
359 // @todo: Do I need this?
360 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
361
362 void clearArchRegs() { actualTC->clearArchRegs(); }
363
364 //
365 // New accessors for new decoder.
366 //
367 uint64_t readIntReg(int reg_idx)
368 { return actualTC->readIntReg(reg_idx); }
369
370 FloatReg readFloatReg(int reg_idx)
371 { return actualTC->readFloatReg(reg_idx); }
372
373 FloatRegBits readFloatRegBits(int reg_idx)
374 { return actualTC->readFloatRegBits(reg_idx); }
375
376 void setIntReg(int reg_idx, uint64_t val)
377 { actualTC->setIntReg(reg_idx, val); }
378
379 void setFloatReg(int reg_idx, FloatReg val)
380 { actualTC->setFloatReg(reg_idx, val); }
381
382 void setFloatRegBits(int reg_idx, FloatRegBits val)
383 { actualTC->setFloatRegBits(reg_idx, val); }
384
385 TheISA::PCState pcState() { return actualTC->pcState(); }
386
387 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
388
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395#if USE_CHECKER
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396 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
| 389 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
|
397#endif
| |
398
399 Addr instAddr() { return actualTC->instAddr(); }
400 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
401 MicroPC microPC() { return actualTC->microPC(); }
402
403 bool readPredicate() { return actualTC->readPredicate(); }
404
405 void setPredicate(bool val)
406 { actualTC->setPredicate(val); }
407
408 MiscReg readMiscRegNoEffect(int misc_reg)
409 { return actualTC->readMiscRegNoEffect(misc_reg); }
410
411 MiscReg readMiscReg(int misc_reg)
412 { return actualTC->readMiscReg(misc_reg); }
413
414 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
415 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
416
417 void setMiscReg(int misc_reg, const MiscReg &val)
418 { return actualTC->setMiscReg(misc_reg, val); }
419
420 int flattenIntIndex(int reg)
421 { return actualTC->flattenIntIndex(reg); }
422
423 int flattenFloatIndex(int reg)
424 { return actualTC->flattenFloatIndex(reg); }
425
426 unsigned readStCondFailures()
427 { return actualTC->readStCondFailures(); }
428
429 void setStCondFailures(unsigned sc_failures)
430 { actualTC->setStCondFailures(sc_failures); }
431
432 // @todo: Fix this!
433 bool misspeculating() { return actualTC->misspeculating(); }
434
435 void syscall(int64_t callnum)
436 { actualTC->syscall(callnum); }
437
438 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
439};
440
441#endif
| 390
391 Addr instAddr() { return actualTC->instAddr(); }
392 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
393 MicroPC microPC() { return actualTC->microPC(); }
394
395 bool readPredicate() { return actualTC->readPredicate(); }
396
397 void setPredicate(bool val)
398 { actualTC->setPredicate(val); }
399
400 MiscReg readMiscRegNoEffect(int misc_reg)
401 { return actualTC->readMiscRegNoEffect(misc_reg); }
402
403 MiscReg readMiscReg(int misc_reg)
404 { return actualTC->readMiscReg(misc_reg); }
405
406 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
407 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
408
409 void setMiscReg(int misc_reg, const MiscReg &val)
410 { return actualTC->setMiscReg(misc_reg, val); }
411
412 int flattenIntIndex(int reg)
413 { return actualTC->flattenIntIndex(reg); }
414
415 int flattenFloatIndex(int reg)
416 { return actualTC->flattenFloatIndex(reg); }
417
418 unsigned readStCondFailures()
419 { return actualTC->readStCondFailures(); }
420
421 void setStCondFailures(unsigned sc_failures)
422 { actualTC->setStCondFailures(sc_failures); }
423
424 // @todo: Fix this!
425 bool misspeculating() { return actualTC->misspeculating(); }
426
427 void syscall(int64_t callnum)
428 { actualTC->syscall(callnum); }
429
430 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
431};
432
433#endif
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