1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include "arch/registers.hh"
35#include "arch/types.hh"
36#include "base/types.hh"
37#include "config/full_system.hh"
38#include "config/the_isa.hh"
39#include "mem/request.hh"
40#include "sim/byteswap.hh"
41#include "sim/faults.hh"
42#include "sim/serialize.hh"
43
44// @todo: Figure out a more architecture independent way to obtain the ITB and
45// DTB pointers.
46namespace TheISA
47{
48 class TLB;
49}
50class BaseCPU;
51class EndQuiesceEvent;
52class Event;
53class TranslatingPort;
54class FunctionalPort;
55class VirtualPort;
56class Process;
57class System;
58namespace TheISA {
59 namespace Kernel {
60 class Statistics;
61 };
62};
63
64/**
65 * ThreadContext is the external interface to all thread state for
66 * anything outside of the CPU. It provides all accessor methods to
67 * state that might be needed by external objects, ranging from
68 * register values to things such as kernel stats. It is an abstract
69 * base class; the CPU can create its own ThreadContext by either
70 * deriving from it, or using the templated ProxyThreadContext.
71 *
72 * The ThreadContext is slightly different than the ExecContext. The
73 * ThreadContext provides access to an individual thread's state; an
74 * ExecContext provides ISA access to the CPU (meaning it is
75 * implicitly multithreaded on SMT systems). Additionally the
76 * ThreadState is an abstract class that exactly defines the
77 * interface; the ExecContext is a more implicit interface that must
78 * be implemented so that the ISA can access whatever state it needs.
79 */
80class ThreadContext
81{
82 protected:
83 typedef TheISA::MachInst MachInst;
84 typedef TheISA::IntReg IntReg;
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
87 typedef TheISA::MiscReg MiscReg;
88 public:
89
90 enum Status
91 {
92 /// Running. Instructions should be executed only when
93 /// the context is in this state.
94 Active,
95
96 /// Temporarily inactive. Entered while waiting for
97 /// synchronization, etc.
98 Suspended,
99
100 /// Permanently shut down. Entered when target executes
101 /// m5exit pseudo-instruction. When all contexts enter
102 /// this state, the simulation will terminate.
103 Halted
104 };
105
106 virtual ~ThreadContext() { };
107
108 virtual BaseCPU *getCpuPtr() = 0;
109
110 virtual int cpuId() = 0;
111
112 virtual int threadId() = 0;
113
114 virtual void setThreadId(int id) = 0;
115
116 virtual int contextId() = 0;
117
118 virtual void setContextId(int id) = 0;
119
120 virtual TheISA::TLB *getITBPtr() = 0;
121
122 virtual TheISA::TLB *getDTBPtr() = 0;
123
124 virtual System *getSystemPtr() = 0;
125
126#if FULL_SYSTEM
127 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
128
129 virtual FunctionalPort *getPhysPort() = 0;
130
131 virtual VirtualPort *getVirtPort() = 0;
132
133 virtual void connectMemPorts(ThreadContext *tc) = 0;
134#else
135 virtual TranslatingPort *getMemPort() = 0;
136
137 virtual Process *getProcessPtr() = 0;
138#endif
139
140 virtual Status status() const = 0;
141
142 virtual void setStatus(Status new_status) = 0;
143
144 /// Set the status to Active. Optional delay indicates number of
145 /// cycles to wait before beginning execution.
146 virtual void activate(int delay = 1) = 0;
147
148 /// Set the status to Suspended.
149 virtual void suspend(int delay = 0) = 0;
150
151 /// Set the status to Halted.
152 virtual void halt(int delay = 0) = 0;
153
154#if FULL_SYSTEM
155 virtual void dumpFuncProfile() = 0;
156#endif
157
158 virtual void takeOverFrom(ThreadContext *old_context) = 0;
159
160 virtual void regStats(const std::string &name) = 0;
161
162 virtual void serialize(std::ostream &os) = 0;
163 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
164
165#if FULL_SYSTEM
166 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
167
168 // Not necessarily the best location for these...
169 // Having an extra function just to read these is obnoxious
170 virtual Tick readLastActivate() = 0;
171 virtual Tick readLastSuspend() = 0;
172
173 virtual void profileClear() = 0;
174 virtual void profileSample() = 0;
175#endif
176
177 // Also somewhat obnoxious. Really only used for the TLB fault.
178 // However, may be quite useful in SPARC.
179 virtual TheISA::MachInst getInst() = 0;
180
181 virtual void copyArchRegs(ThreadContext *tc) = 0;
182
183 virtual void clearArchRegs() = 0;
184
185 //
186 // New accessors for new decoder.
187 //
188 virtual uint64_t readIntReg(int reg_idx) = 0;
189
190 virtual FloatReg readFloatReg(int reg_idx) = 0;
191
192 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
193
194 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
195
196 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
197
198 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
199
200 virtual uint64_t readPC() = 0;
201
202 virtual void setPC(uint64_t val) = 0;
203
204 virtual uint64_t readNextPC() = 0;
205
206 virtual void setNextPC(uint64_t val) = 0;
207
208 virtual uint64_t readNextNPC() = 0;
209
210 virtual void setNextNPC(uint64_t val) = 0;
211
212 virtual uint64_t readMicroPC() = 0;
213
214 virtual void setMicroPC(uint64_t val) = 0;
215
216 virtual uint64_t readNextMicroPC() = 0;
217
218 virtual void setNextMicroPC(uint64_t val) = 0;
219
220 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
221
222 virtual MiscReg readMiscReg(int misc_reg) = 0;
223
224 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
225
226 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
227
228 virtual int flattenIntIndex(int reg) = 0;
229 virtual int flattenFloatIndex(int reg) = 0;
230
231 virtual uint64_t
232 readRegOtherThread(int misc_reg, ThreadID tid)
233 {
234 return 0;
235 }
236
237 virtual void
238 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
239 {
240 }
241
242 // Also not necessarily the best location for these two. Hopefully will go
243 // away once we decide upon where st cond failures goes.
244 virtual unsigned readStCondFailures() = 0;
245
246 virtual void setStCondFailures(unsigned sc_failures) = 0;
247
248 // Only really makes sense for old CPU model. Still could be useful though.
249 virtual bool misspeculating() = 0;
250
251#if !FULL_SYSTEM
252 // Same with st cond failures.
253 virtual Counter readFuncExeInst() = 0;
254
255 virtual void syscall(int64_t callnum) = 0;
256
257 // This function exits the thread context in the CPU and returns
258 // 1 if the CPU has no more active threads (meaning it's OK to exit);
259 // Used in syscall-emulation mode when a thread calls the exit syscall.
260 virtual int exit() { return 1; };
261#endif
262
263 /** function to compare two thread contexts (for debugging) */
264 static void compare(ThreadContext *one, ThreadContext *two);
265};
266
267/**
268 * ProxyThreadContext class that provides a way to implement a
269 * ThreadContext without having to derive from it. ThreadContext is an
270 * abstract class, so anything that derives from it and uses its
271 * interface will pay the overhead of virtual function calls. This
272 * class is created to enable a user-defined Thread object to be used
273 * wherever ThreadContexts are used, without paying the overhead of
274 * virtual function calls when it is used by itself. See
275 * simple_thread.hh for an example of this.
276 */
277template <class TC>
278class ProxyThreadContext : public ThreadContext
279{
280 public:
281 ProxyThreadContext(TC *actual_tc)
282 { actualTC = actual_tc; }
283
284 private:
285 TC *actualTC;
286
287 public:
288
289 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
290
291 int cpuId() { return actualTC->cpuId(); }
292
293 int threadId() { return actualTC->threadId(); }
294
295 void setThreadId(int id) { return actualTC->setThreadId(id); }
296
297 int contextId() { return actualTC->contextId(); }
298
299 void setContextId(int id) { actualTC->setContextId(id); }
300
301 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
302
303 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
304
305 System *getSystemPtr() { return actualTC->getSystemPtr(); }
306
307#if FULL_SYSTEM
308 TheISA::Kernel::Statistics *getKernelStats()
309 { return actualTC->getKernelStats(); }
310
311 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
312
313 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
314
315 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
316#else
317 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
318
319 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
320#endif
321
322 Status status() const { return actualTC->status(); }
323
324 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
325
326 /// Set the status to Active. Optional delay indicates number of
327 /// cycles to wait before beginning execution.
328 void activate(int delay = 1) { actualTC->activate(delay); }
329
330 /// Set the status to Suspended.
331 void suspend(int delay = 0) { actualTC->suspend(); }
332
333 /// Set the status to Halted.
334 void halt(int delay = 0) { actualTC->halt(); }
335
336#if FULL_SYSTEM
337 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
338#endif
339
340 void takeOverFrom(ThreadContext *oldContext)
341 { actualTC->takeOverFrom(oldContext); }
342
343 void regStats(const std::string &name) { actualTC->regStats(name); }
344
345 void serialize(std::ostream &os) { actualTC->serialize(os); }
346 void unserialize(Checkpoint *cp, const std::string §ion)
347 { actualTC->unserialize(cp, section); }
348
349#if FULL_SYSTEM
350 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
351
352 Tick readLastActivate() { return actualTC->readLastActivate(); }
353 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
354
355 void profileClear() { return actualTC->profileClear(); }
356 void profileSample() { return actualTC->profileSample(); }
357#endif
358 // @todo: Do I need this?
359 MachInst getInst() { return actualTC->getInst(); }
360
361 // @todo: Do I need this?
362 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
363
364 void clearArchRegs() { actualTC->clearArchRegs(); }
365
366 //
367 // New accessors for new decoder.
368 //
369 uint64_t readIntReg(int reg_idx)
370 { return actualTC->readIntReg(reg_idx); }
371
372 FloatReg readFloatReg(int reg_idx)
373 { return actualTC->readFloatReg(reg_idx); }
374
375 FloatRegBits readFloatRegBits(int reg_idx)
376 { return actualTC->readFloatRegBits(reg_idx); }
377
378 void setIntReg(int reg_idx, uint64_t val)
379 { actualTC->setIntReg(reg_idx, val); }
380
381 void setFloatReg(int reg_idx, FloatReg val)
382 { actualTC->setFloatReg(reg_idx, val); }
383
384 void setFloatRegBits(int reg_idx, FloatRegBits val)
385 { actualTC->setFloatRegBits(reg_idx, val); }
386
387 uint64_t readPC() { return actualTC->readPC(); }
388
389 void setPC(uint64_t val) { actualTC->setPC(val); }
390
391 uint64_t readNextPC() { return actualTC->readNextPC(); }
392
393 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
394
395 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
396
397 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
398
399 uint64_t readMicroPC() { return actualTC->readMicroPC(); }
400
401 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
402
403 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
404
405 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
406
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include "arch/registers.hh"
35#include "arch/types.hh"
36#include "base/types.hh"
37#include "config/full_system.hh"
38#include "config/the_isa.hh"
39#include "mem/request.hh"
40#include "sim/byteswap.hh"
41#include "sim/faults.hh"
42#include "sim/serialize.hh"
43
44// @todo: Figure out a more architecture independent way to obtain the ITB and
45// DTB pointers.
46namespace TheISA
47{
48 class TLB;
49}
50class BaseCPU;
51class EndQuiesceEvent;
52class Event;
53class TranslatingPort;
54class FunctionalPort;
55class VirtualPort;
56class Process;
57class System;
58namespace TheISA {
59 namespace Kernel {
60 class Statistics;
61 };
62};
63
64/**
65 * ThreadContext is the external interface to all thread state for
66 * anything outside of the CPU. It provides all accessor methods to
67 * state that might be needed by external objects, ranging from
68 * register values to things such as kernel stats. It is an abstract
69 * base class; the CPU can create its own ThreadContext by either
70 * deriving from it, or using the templated ProxyThreadContext.
71 *
72 * The ThreadContext is slightly different than the ExecContext. The
73 * ThreadContext provides access to an individual thread's state; an
74 * ExecContext provides ISA access to the CPU (meaning it is
75 * implicitly multithreaded on SMT systems). Additionally the
76 * ThreadState is an abstract class that exactly defines the
77 * interface; the ExecContext is a more implicit interface that must
78 * be implemented so that the ISA can access whatever state it needs.
79 */
80class ThreadContext
81{
82 protected:
83 typedef TheISA::MachInst MachInst;
84 typedef TheISA::IntReg IntReg;
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
87 typedef TheISA::MiscReg MiscReg;
88 public:
89
90 enum Status
91 {
92 /// Running. Instructions should be executed only when
93 /// the context is in this state.
94 Active,
95
96 /// Temporarily inactive. Entered while waiting for
97 /// synchronization, etc.
98 Suspended,
99
100 /// Permanently shut down. Entered when target executes
101 /// m5exit pseudo-instruction. When all contexts enter
102 /// this state, the simulation will terminate.
103 Halted
104 };
105
106 virtual ~ThreadContext() { };
107
108 virtual BaseCPU *getCpuPtr() = 0;
109
110 virtual int cpuId() = 0;
111
112 virtual int threadId() = 0;
113
114 virtual void setThreadId(int id) = 0;
115
116 virtual int contextId() = 0;
117
118 virtual void setContextId(int id) = 0;
119
120 virtual TheISA::TLB *getITBPtr() = 0;
121
122 virtual TheISA::TLB *getDTBPtr() = 0;
123
124 virtual System *getSystemPtr() = 0;
125
126#if FULL_SYSTEM
127 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
128
129 virtual FunctionalPort *getPhysPort() = 0;
130
131 virtual VirtualPort *getVirtPort() = 0;
132
133 virtual void connectMemPorts(ThreadContext *tc) = 0;
134#else
135 virtual TranslatingPort *getMemPort() = 0;
136
137 virtual Process *getProcessPtr() = 0;
138#endif
139
140 virtual Status status() const = 0;
141
142 virtual void setStatus(Status new_status) = 0;
143
144 /// Set the status to Active. Optional delay indicates number of
145 /// cycles to wait before beginning execution.
146 virtual void activate(int delay = 1) = 0;
147
148 /// Set the status to Suspended.
149 virtual void suspend(int delay = 0) = 0;
150
151 /// Set the status to Halted.
152 virtual void halt(int delay = 0) = 0;
153
154#if FULL_SYSTEM
155 virtual void dumpFuncProfile() = 0;
156#endif
157
158 virtual void takeOverFrom(ThreadContext *old_context) = 0;
159
160 virtual void regStats(const std::string &name) = 0;
161
162 virtual void serialize(std::ostream &os) = 0;
163 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
164
165#if FULL_SYSTEM
166 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
167
168 // Not necessarily the best location for these...
169 // Having an extra function just to read these is obnoxious
170 virtual Tick readLastActivate() = 0;
171 virtual Tick readLastSuspend() = 0;
172
173 virtual void profileClear() = 0;
174 virtual void profileSample() = 0;
175#endif
176
177 // Also somewhat obnoxious. Really only used for the TLB fault.
178 // However, may be quite useful in SPARC.
179 virtual TheISA::MachInst getInst() = 0;
180
181 virtual void copyArchRegs(ThreadContext *tc) = 0;
182
183 virtual void clearArchRegs() = 0;
184
185 //
186 // New accessors for new decoder.
187 //
188 virtual uint64_t readIntReg(int reg_idx) = 0;
189
190 virtual FloatReg readFloatReg(int reg_idx) = 0;
191
192 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
193
194 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
195
196 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
197
198 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
199
200 virtual uint64_t readPC() = 0;
201
202 virtual void setPC(uint64_t val) = 0;
203
204 virtual uint64_t readNextPC() = 0;
205
206 virtual void setNextPC(uint64_t val) = 0;
207
208 virtual uint64_t readNextNPC() = 0;
209
210 virtual void setNextNPC(uint64_t val) = 0;
211
212 virtual uint64_t readMicroPC() = 0;
213
214 virtual void setMicroPC(uint64_t val) = 0;
215
216 virtual uint64_t readNextMicroPC() = 0;
217
218 virtual void setNextMicroPC(uint64_t val) = 0;
219
220 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
221
222 virtual MiscReg readMiscReg(int misc_reg) = 0;
223
224 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
225
226 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
227
228 virtual int flattenIntIndex(int reg) = 0;
229 virtual int flattenFloatIndex(int reg) = 0;
230
231 virtual uint64_t
232 readRegOtherThread(int misc_reg, ThreadID tid)
233 {
234 return 0;
235 }
236
237 virtual void
238 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
239 {
240 }
241
242 // Also not necessarily the best location for these two. Hopefully will go
243 // away once we decide upon where st cond failures goes.
244 virtual unsigned readStCondFailures() = 0;
245
246 virtual void setStCondFailures(unsigned sc_failures) = 0;
247
248 // Only really makes sense for old CPU model. Still could be useful though.
249 virtual bool misspeculating() = 0;
250
251#if !FULL_SYSTEM
252 // Same with st cond failures.
253 virtual Counter readFuncExeInst() = 0;
254
255 virtual void syscall(int64_t callnum) = 0;
256
257 // This function exits the thread context in the CPU and returns
258 // 1 if the CPU has no more active threads (meaning it's OK to exit);
259 // Used in syscall-emulation mode when a thread calls the exit syscall.
260 virtual int exit() { return 1; };
261#endif
262
263 /** function to compare two thread contexts (for debugging) */
264 static void compare(ThreadContext *one, ThreadContext *two);
265};
266
267/**
268 * ProxyThreadContext class that provides a way to implement a
269 * ThreadContext without having to derive from it. ThreadContext is an
270 * abstract class, so anything that derives from it and uses its
271 * interface will pay the overhead of virtual function calls. This
272 * class is created to enable a user-defined Thread object to be used
273 * wherever ThreadContexts are used, without paying the overhead of
274 * virtual function calls when it is used by itself. See
275 * simple_thread.hh for an example of this.
276 */
277template <class TC>
278class ProxyThreadContext : public ThreadContext
279{
280 public:
281 ProxyThreadContext(TC *actual_tc)
282 { actualTC = actual_tc; }
283
284 private:
285 TC *actualTC;
286
287 public:
288
289 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
290
291 int cpuId() { return actualTC->cpuId(); }
292
293 int threadId() { return actualTC->threadId(); }
294
295 void setThreadId(int id) { return actualTC->setThreadId(id); }
296
297 int contextId() { return actualTC->contextId(); }
298
299 void setContextId(int id) { actualTC->setContextId(id); }
300
301 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
302
303 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
304
305 System *getSystemPtr() { return actualTC->getSystemPtr(); }
306
307#if FULL_SYSTEM
308 TheISA::Kernel::Statistics *getKernelStats()
309 { return actualTC->getKernelStats(); }
310
311 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
312
313 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
314
315 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
316#else
317 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
318
319 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
320#endif
321
322 Status status() const { return actualTC->status(); }
323
324 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
325
326 /// Set the status to Active. Optional delay indicates number of
327 /// cycles to wait before beginning execution.
328 void activate(int delay = 1) { actualTC->activate(delay); }
329
330 /// Set the status to Suspended.
331 void suspend(int delay = 0) { actualTC->suspend(); }
332
333 /// Set the status to Halted.
334 void halt(int delay = 0) { actualTC->halt(); }
335
336#if FULL_SYSTEM
337 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
338#endif
339
340 void takeOverFrom(ThreadContext *oldContext)
341 { actualTC->takeOverFrom(oldContext); }
342
343 void regStats(const std::string &name) { actualTC->regStats(name); }
344
345 void serialize(std::ostream &os) { actualTC->serialize(os); }
346 void unserialize(Checkpoint *cp, const std::string §ion)
347 { actualTC->unserialize(cp, section); }
348
349#if FULL_SYSTEM
350 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
351
352 Tick readLastActivate() { return actualTC->readLastActivate(); }
353 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
354
355 void profileClear() { return actualTC->profileClear(); }
356 void profileSample() { return actualTC->profileSample(); }
357#endif
358 // @todo: Do I need this?
359 MachInst getInst() { return actualTC->getInst(); }
360
361 // @todo: Do I need this?
362 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
363
364 void clearArchRegs() { actualTC->clearArchRegs(); }
365
366 //
367 // New accessors for new decoder.
368 //
369 uint64_t readIntReg(int reg_idx)
370 { return actualTC->readIntReg(reg_idx); }
371
372 FloatReg readFloatReg(int reg_idx)
373 { return actualTC->readFloatReg(reg_idx); }
374
375 FloatRegBits readFloatRegBits(int reg_idx)
376 { return actualTC->readFloatRegBits(reg_idx); }
377
378 void setIntReg(int reg_idx, uint64_t val)
379 { actualTC->setIntReg(reg_idx, val); }
380
381 void setFloatReg(int reg_idx, FloatReg val)
382 { actualTC->setFloatReg(reg_idx, val); }
383
384 void setFloatRegBits(int reg_idx, FloatRegBits val)
385 { actualTC->setFloatRegBits(reg_idx, val); }
386
387 uint64_t readPC() { return actualTC->readPC(); }
388
389 void setPC(uint64_t val) { actualTC->setPC(val); }
390
391 uint64_t readNextPC() { return actualTC->readNextPC(); }
392
393 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
394
395 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
396
397 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
398
399 uint64_t readMicroPC() { return actualTC->readMicroPC(); }
400
401 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
402
403 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
404
405 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
406
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