1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include "arch/regfile.hh"
35#include "arch/syscallreturn.hh"
36#include "arch/types.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
39#include "sim/faults.hh"
40#include "sim/host.hh"
41#include "sim/serialize.hh"
42#include "sim/byteswap.hh"
43
44// @todo: Figure out a more architecture independent way to obtain the ITB and
45// DTB pointers.
46namespace TheISA
47{
48 class DTB;
49 class ITB;
50}
51class BaseCPU;
52class EndQuiesceEvent;
53class Event;
54class TranslatingPort;
55class FunctionalPort;
56class VirtualPort;
57class Process;
58class System;
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include "arch/regfile.hh"
35#include "arch/syscallreturn.hh"
36#include "arch/types.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
39#include "sim/faults.hh"
40#include "sim/host.hh"
41#include "sim/serialize.hh"
42#include "sim/byteswap.hh"
43
44// @todo: Figure out a more architecture independent way to obtain the ITB and
45// DTB pointers.
46namespace TheISA
47{
48 class DTB;
49 class ITB;
50}
51class BaseCPU;
52class EndQuiesceEvent;
53class Event;
54class TranslatingPort;
55class FunctionalPort;
56class VirtualPort;
57class Process;
58class System;
|
59namespace Kernel {
60 class Statistics;
| 59namespace TheISA {
60 namespace Kernel {
61 class Statistics;
62 };
|
61};
62
63/**
64 * ThreadContext is the external interface to all thread state for
65 * anything outside of the CPU. It provides all accessor methods to
66 * state that might be needed by external objects, ranging from
67 * register values to things such as kernel stats. It is an abstract
68 * base class; the CPU can create its own ThreadContext by either
69 * deriving from it, or using the templated ProxyThreadContext.
70 *
71 * The ThreadContext is slightly different than the ExecContext. The
72 * ThreadContext provides access to an individual thread's state; an
73 * ExecContext provides ISA access to the CPU (meaning it is
74 * implicitly multithreaded on SMT systems). Additionally the
75 * ThreadState is an abstract class that exactly defines the
76 * interface; the ExecContext is a more implicit interface that must
77 * be implemented so that the ISA can access whatever state it needs.
78 */
79class ThreadContext
80{
81 protected:
82 typedef TheISA::RegFile RegFile;
83 typedef TheISA::MachInst MachInst;
84 typedef TheISA::IntReg IntReg;
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
87 typedef TheISA::MiscRegFile MiscRegFile;
88 typedef TheISA::MiscReg MiscReg;
89 public:
90 enum Status
91 {
92 /// Initialized but not running yet. All CPUs start in
93 /// this state, but most transition to Active on cycle 1.
94 /// In MP or SMT systems, non-primary contexts will stay
95 /// in this state until a thread is assigned to them.
96 Unallocated,
97
98 /// Running. Instructions should be executed only when
99 /// the context is in this state.
100 Active,
101
102 /// Temporarily inactive. Entered while waiting for
103 /// synchronization, etc.
104 Suspended,
105
106 /// Permanently shut down. Entered when target executes
107 /// m5exit pseudo-instruction. When all contexts enter
108 /// this state, the simulation will terminate.
109 Halted
110 };
111
112 virtual ~ThreadContext() { };
113
114 virtual BaseCPU *getCpuPtr() = 0;
115
116 virtual void setCpuId(int id) = 0;
117
118 virtual int readCpuId() = 0;
119
120#if FULL_SYSTEM
121 virtual System *getSystemPtr() = 0;
122
123 virtual TheISA::ITB *getITBPtr() = 0;
124
125 virtual TheISA::DTB *getDTBPtr() = 0;
126
| 63};
64
65/**
66 * ThreadContext is the external interface to all thread state for
67 * anything outside of the CPU. It provides all accessor methods to
68 * state that might be needed by external objects, ranging from
69 * register values to things such as kernel stats. It is an abstract
70 * base class; the CPU can create its own ThreadContext by either
71 * deriving from it, or using the templated ProxyThreadContext.
72 *
73 * The ThreadContext is slightly different than the ExecContext. The
74 * ThreadContext provides access to an individual thread's state; an
75 * ExecContext provides ISA access to the CPU (meaning it is
76 * implicitly multithreaded on SMT systems). Additionally the
77 * ThreadState is an abstract class that exactly defines the
78 * interface; the ExecContext is a more implicit interface that must
79 * be implemented so that the ISA can access whatever state it needs.
80 */
81class ThreadContext
82{
83 protected:
84 typedef TheISA::RegFile RegFile;
85 typedef TheISA::MachInst MachInst;
86 typedef TheISA::IntReg IntReg;
87 typedef TheISA::FloatReg FloatReg;
88 typedef TheISA::FloatRegBits FloatRegBits;
89 typedef TheISA::MiscRegFile MiscRegFile;
90 typedef TheISA::MiscReg MiscReg;
91 public:
92 enum Status
93 {
94 /// Initialized but not running yet. All CPUs start in
95 /// this state, but most transition to Active on cycle 1.
96 /// In MP or SMT systems, non-primary contexts will stay
97 /// in this state until a thread is assigned to them.
98 Unallocated,
99
100 /// Running. Instructions should be executed only when
101 /// the context is in this state.
102 Active,
103
104 /// Temporarily inactive. Entered while waiting for
105 /// synchronization, etc.
106 Suspended,
107
108 /// Permanently shut down. Entered when target executes
109 /// m5exit pseudo-instruction. When all contexts enter
110 /// this state, the simulation will terminate.
111 Halted
112 };
113
114 virtual ~ThreadContext() { };
115
116 virtual BaseCPU *getCpuPtr() = 0;
117
118 virtual void setCpuId(int id) = 0;
119
120 virtual int readCpuId() = 0;
121
122#if FULL_SYSTEM
123 virtual System *getSystemPtr() = 0;
124
125 virtual TheISA::ITB *getITBPtr() = 0;
126
127 virtual TheISA::DTB *getDTBPtr() = 0;
128
|
127 virtual Kernel::Statistics *getKernelStats() = 0;
| 129 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
|
128
129 virtual FunctionalPort *getPhysPort() = 0;
130
131 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
132
133 virtual void delVirtPort(VirtualPort *vp) = 0;
134#else
135 virtual TranslatingPort *getMemPort() = 0;
136
137 virtual Process *getProcessPtr() = 0;
138#endif
139
140 virtual Status status() const = 0;
141
142 virtual void setStatus(Status new_status) = 0;
143
144 /// Set the status to Active. Optional delay indicates number of
145 /// cycles to wait before beginning execution.
146 virtual void activate(int delay = 1) = 0;
147
148 /// Set the status to Suspended.
149 virtual void suspend() = 0;
150
151 /// Set the status to Unallocated.
152 virtual void deallocate(int delay = 0) = 0;
153
154 /// Set the status to Halted.
155 virtual void halt() = 0;
156
157#if FULL_SYSTEM
158 virtual void dumpFuncProfile() = 0;
159#endif
160
161 virtual void takeOverFrom(ThreadContext *old_context) = 0;
162
163 virtual void regStats(const std::string &name) = 0;
164
165 virtual void serialize(std::ostream &os) = 0;
166 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
167
168#if FULL_SYSTEM
169 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
170
171 // Not necessarily the best location for these...
172 // Having an extra function just to read these is obnoxious
173 virtual Tick readLastActivate() = 0;
174 virtual Tick readLastSuspend() = 0;
175
176 virtual void profileClear() = 0;
177 virtual void profileSample() = 0;
178#endif
179
180 virtual int getThreadNum() = 0;
181
182 // Also somewhat obnoxious. Really only used for the TLB fault.
183 // However, may be quite useful in SPARC.
184 virtual TheISA::MachInst getInst() = 0;
185
186 virtual void copyArchRegs(ThreadContext *tc) = 0;
187
188 virtual void clearArchRegs() = 0;
189
190 //
191 // New accessors for new decoder.
192 //
193 virtual uint64_t readIntReg(int reg_idx) = 0;
194
195 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
196
197 virtual FloatReg readFloatReg(int reg_idx) = 0;
198
199 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
200
201 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
202
203 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
204
205 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
206
207 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
208
209 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
210
211 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
212
213 virtual uint64_t readPC() = 0;
214
215 virtual void setPC(uint64_t val) = 0;
216
217 virtual uint64_t readNextPC() = 0;
218
219 virtual void setNextPC(uint64_t val) = 0;
220
221 virtual uint64_t readNextNPC() = 0;
222
223 virtual void setNextNPC(uint64_t val) = 0;
224
225 virtual MiscReg readMiscReg(int misc_reg) = 0;
226
227 virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
228
229 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
230
231 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
232
233 // Also not necessarily the best location for these two. Hopefully will go
234 // away once we decide upon where st cond failures goes.
235 virtual unsigned readStCondFailures() = 0;
236
237 virtual void setStCondFailures(unsigned sc_failures) = 0;
238
239 // Only really makes sense for old CPU model. Still could be useful though.
240 virtual bool misspeculating() = 0;
241
242#if !FULL_SYSTEM
243 virtual IntReg getSyscallArg(int i) = 0;
244
245 // used to shift args for indirect syscall
246 virtual void setSyscallArg(int i, IntReg val) = 0;
247
248 virtual void setSyscallReturn(SyscallReturn return_value) = 0;
249
250 // Same with st cond failures.
251 virtual Counter readFuncExeInst() = 0;
252
253 // This function exits the thread context in the CPU and returns
254 // 1 if the CPU has no more active threads (meaning it's OK to exit);
255 // Used in syscall-emulation mode when a thread calls the exit syscall.
256 virtual int exit() { return 1; };
257#endif
258
259 virtual void changeRegFileContext(TheISA::RegContextParam param,
260 TheISA::RegContextVal val) = 0;
261};
262
263/**
264 * ProxyThreadContext class that provides a way to implement a
265 * ThreadContext without having to derive from it. ThreadContext is an
266 * abstract class, so anything that derives from it and uses its
267 * interface will pay the overhead of virtual function calls. This
268 * class is created to enable a user-defined Thread object to be used
269 * wherever ThreadContexts are used, without paying the overhead of
270 * virtual function calls when it is used by itself. See
271 * simple_thread.hh for an example of this.
272 */
273template <class TC>
274class ProxyThreadContext : public ThreadContext
275{
276 public:
277 ProxyThreadContext(TC *actual_tc)
278 { actualTC = actual_tc; }
279
280 private:
281 TC *actualTC;
282
283 public:
284
285 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
286
287 void setCpuId(int id) { actualTC->setCpuId(id); }
288
289 int readCpuId() { return actualTC->readCpuId(); }
290
291#if FULL_SYSTEM
292 System *getSystemPtr() { return actualTC->getSystemPtr(); }
293
294 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
295
296 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
297
| 130
131 virtual FunctionalPort *getPhysPort() = 0;
132
133 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
134
135 virtual void delVirtPort(VirtualPort *vp) = 0;
136#else
137 virtual TranslatingPort *getMemPort() = 0;
138
139 virtual Process *getProcessPtr() = 0;
140#endif
141
142 virtual Status status() const = 0;
143
144 virtual void setStatus(Status new_status) = 0;
145
146 /// Set the status to Active. Optional delay indicates number of
147 /// cycles to wait before beginning execution.
148 virtual void activate(int delay = 1) = 0;
149
150 /// Set the status to Suspended.
151 virtual void suspend() = 0;
152
153 /// Set the status to Unallocated.
154 virtual void deallocate(int delay = 0) = 0;
155
156 /// Set the status to Halted.
157 virtual void halt() = 0;
158
159#if FULL_SYSTEM
160 virtual void dumpFuncProfile() = 0;
161#endif
162
163 virtual void takeOverFrom(ThreadContext *old_context) = 0;
164
165 virtual void regStats(const std::string &name) = 0;
166
167 virtual void serialize(std::ostream &os) = 0;
168 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
169
170#if FULL_SYSTEM
171 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
172
173 // Not necessarily the best location for these...
174 // Having an extra function just to read these is obnoxious
175 virtual Tick readLastActivate() = 0;
176 virtual Tick readLastSuspend() = 0;
177
178 virtual void profileClear() = 0;
179 virtual void profileSample() = 0;
180#endif
181
182 virtual int getThreadNum() = 0;
183
184 // Also somewhat obnoxious. Really only used for the TLB fault.
185 // However, may be quite useful in SPARC.
186 virtual TheISA::MachInst getInst() = 0;
187
188 virtual void copyArchRegs(ThreadContext *tc) = 0;
189
190 virtual void clearArchRegs() = 0;
191
192 //
193 // New accessors for new decoder.
194 //
195 virtual uint64_t readIntReg(int reg_idx) = 0;
196
197 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
198
199 virtual FloatReg readFloatReg(int reg_idx) = 0;
200
201 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
202
203 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
204
205 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
206
207 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
208
209 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
210
211 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
212
213 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
214
215 virtual uint64_t readPC() = 0;
216
217 virtual void setPC(uint64_t val) = 0;
218
219 virtual uint64_t readNextPC() = 0;
220
221 virtual void setNextPC(uint64_t val) = 0;
222
223 virtual uint64_t readNextNPC() = 0;
224
225 virtual void setNextNPC(uint64_t val) = 0;
226
227 virtual MiscReg readMiscReg(int misc_reg) = 0;
228
229 virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
230
231 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
232
233 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
234
235 // Also not necessarily the best location for these two. Hopefully will go
236 // away once we decide upon where st cond failures goes.
237 virtual unsigned readStCondFailures() = 0;
238
239 virtual void setStCondFailures(unsigned sc_failures) = 0;
240
241 // Only really makes sense for old CPU model. Still could be useful though.
242 virtual bool misspeculating() = 0;
243
244#if !FULL_SYSTEM
245 virtual IntReg getSyscallArg(int i) = 0;
246
247 // used to shift args for indirect syscall
248 virtual void setSyscallArg(int i, IntReg val) = 0;
249
250 virtual void setSyscallReturn(SyscallReturn return_value) = 0;
251
252 // Same with st cond failures.
253 virtual Counter readFuncExeInst() = 0;
254
255 // This function exits the thread context in the CPU and returns
256 // 1 if the CPU has no more active threads (meaning it's OK to exit);
257 // Used in syscall-emulation mode when a thread calls the exit syscall.
258 virtual int exit() { return 1; };
259#endif
260
261 virtual void changeRegFileContext(TheISA::RegContextParam param,
262 TheISA::RegContextVal val) = 0;
263};
264
265/**
266 * ProxyThreadContext class that provides a way to implement a
267 * ThreadContext without having to derive from it. ThreadContext is an
268 * abstract class, so anything that derives from it and uses its
269 * interface will pay the overhead of virtual function calls. This
270 * class is created to enable a user-defined Thread object to be used
271 * wherever ThreadContexts are used, without paying the overhead of
272 * virtual function calls when it is used by itself. See
273 * simple_thread.hh for an example of this.
274 */
275template <class TC>
276class ProxyThreadContext : public ThreadContext
277{
278 public:
279 ProxyThreadContext(TC *actual_tc)
280 { actualTC = actual_tc; }
281
282 private:
283 TC *actualTC;
284
285 public:
286
287 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
288
289 void setCpuId(int id) { actualTC->setCpuId(id); }
290
291 int readCpuId() { return actualTC->readCpuId(); }
292
293#if FULL_SYSTEM
294 System *getSystemPtr() { return actualTC->getSystemPtr(); }
295
296 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
297
298 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
299
|
298 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
| 300 TheISA::Kernel::Statistics *getKernelStats()
301 { return actualTC->getKernelStats(); }
|
299
300 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
301
302 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
303
304 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
305#else
306 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
307
308 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
309#endif
310
311 Status status() const { return actualTC->status(); }
312
313 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
314
315 /// Set the status to Active. Optional delay indicates number of
316 /// cycles to wait before beginning execution.
317 void activate(int delay = 1) { actualTC->activate(delay); }
318
319 /// Set the status to Suspended.
320 void suspend() { actualTC->suspend(); }
321
322 /// Set the status to Unallocated.
323 void deallocate(int delay = 0) { actualTC->deallocate(); }
324
325 /// Set the status to Halted.
326 void halt() { actualTC->halt(); }
327
328#if FULL_SYSTEM
329 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
330#endif
331
332 void takeOverFrom(ThreadContext *oldContext)
333 { actualTC->takeOverFrom(oldContext); }
334
335 void regStats(const std::string &name) { actualTC->regStats(name); }
336
337 void serialize(std::ostream &os) { actualTC->serialize(os); }
338 void unserialize(Checkpoint *cp, const std::string §ion)
339 { actualTC->unserialize(cp, section); }
340
341#if FULL_SYSTEM
342 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
343
344 Tick readLastActivate() { return actualTC->readLastActivate(); }
345 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
346
347 void profileClear() { return actualTC->profileClear(); }
348 void profileSample() { return actualTC->profileSample(); }
349#endif
350
351 int getThreadNum() { return actualTC->getThreadNum(); }
352
353 // @todo: Do I need this?
354 MachInst getInst() { return actualTC->getInst(); }
355
356 // @todo: Do I need this?
357 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
358
359 void clearArchRegs() { actualTC->clearArchRegs(); }
360
361 //
362 // New accessors for new decoder.
363 //
364 uint64_t readIntReg(int reg_idx)
365 { return actualTC->readIntReg(reg_idx); }
366
367 FloatReg readFloatReg(int reg_idx, int width)
368 { return actualTC->readFloatReg(reg_idx, width); }
369
370 FloatReg readFloatReg(int reg_idx)
371 { return actualTC->readFloatReg(reg_idx); }
372
373 FloatRegBits readFloatRegBits(int reg_idx, int width)
374 { return actualTC->readFloatRegBits(reg_idx, width); }
375
376 FloatRegBits readFloatRegBits(int reg_idx)
377 { return actualTC->readFloatRegBits(reg_idx); }
378
379 void setIntReg(int reg_idx, uint64_t val)
380 { actualTC->setIntReg(reg_idx, val); }
381
382 void setFloatReg(int reg_idx, FloatReg val, int width)
383 { actualTC->setFloatReg(reg_idx, val, width); }
384
385 void setFloatReg(int reg_idx, FloatReg val)
386 { actualTC->setFloatReg(reg_idx, val); }
387
388 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
389 { actualTC->setFloatRegBits(reg_idx, val, width); }
390
391 void setFloatRegBits(int reg_idx, FloatRegBits val)
392 { actualTC->setFloatRegBits(reg_idx, val); }
393
394 uint64_t readPC() { return actualTC->readPC(); }
395
396 void setPC(uint64_t val) { actualTC->setPC(val); }
397
398 uint64_t readNextPC() { return actualTC->readNextPC(); }
399
400 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
401
402 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
403
404 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
405
406 MiscReg readMiscReg(int misc_reg)
407 { return actualTC->readMiscReg(misc_reg); }
408
409 MiscReg readMiscRegWithEffect(int misc_reg)
410 { return actualTC->readMiscRegWithEffect(misc_reg); }
411
412 void setMiscReg(int misc_reg, const MiscReg &val)
413 { return actualTC->setMiscReg(misc_reg, val); }
414
415 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
416 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
417
418 unsigned readStCondFailures()
419 { return actualTC->readStCondFailures(); }
420
421 void setStCondFailures(unsigned sc_failures)
422 { actualTC->setStCondFailures(sc_failures); }
423
424 // @todo: Fix this!
425 bool misspeculating() { return actualTC->misspeculating(); }
426
427#if !FULL_SYSTEM
428 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
429
430 // used to shift args for indirect syscall
431 void setSyscallArg(int i, IntReg val)
432 { actualTC->setSyscallArg(i, val); }
433
434 void setSyscallReturn(SyscallReturn return_value)
435 { actualTC->setSyscallReturn(return_value); }
436
437 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
438#endif
439
440 void changeRegFileContext(TheISA::RegContextParam param,
441 TheISA::RegContextVal val)
442 {
443 actualTC->changeRegFileContext(param, val);
444 }
445};
446
447#endif
| 302
303 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
304
305 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
306
307 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
308#else
309 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
310
311 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
312#endif
313
314 Status status() const { return actualTC->status(); }
315
316 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
317
318 /// Set the status to Active. Optional delay indicates number of
319 /// cycles to wait before beginning execution.
320 void activate(int delay = 1) { actualTC->activate(delay); }
321
322 /// Set the status to Suspended.
323 void suspend() { actualTC->suspend(); }
324
325 /// Set the status to Unallocated.
326 void deallocate(int delay = 0) { actualTC->deallocate(); }
327
328 /// Set the status to Halted.
329 void halt() { actualTC->halt(); }
330
331#if FULL_SYSTEM
332 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
333#endif
334
335 void takeOverFrom(ThreadContext *oldContext)
336 { actualTC->takeOverFrom(oldContext); }
337
338 void regStats(const std::string &name) { actualTC->regStats(name); }
339
340 void serialize(std::ostream &os) { actualTC->serialize(os); }
341 void unserialize(Checkpoint *cp, const std::string §ion)
342 { actualTC->unserialize(cp, section); }
343
344#if FULL_SYSTEM
345 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
346
347 Tick readLastActivate() { return actualTC->readLastActivate(); }
348 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
349
350 void profileClear() { return actualTC->profileClear(); }
351 void profileSample() { return actualTC->profileSample(); }
352#endif
353
354 int getThreadNum() { return actualTC->getThreadNum(); }
355
356 // @todo: Do I need this?
357 MachInst getInst() { return actualTC->getInst(); }
358
359 // @todo: Do I need this?
360 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
361
362 void clearArchRegs() { actualTC->clearArchRegs(); }
363
364 //
365 // New accessors for new decoder.
366 //
367 uint64_t readIntReg(int reg_idx)
368 { return actualTC->readIntReg(reg_idx); }
369
370 FloatReg readFloatReg(int reg_idx, int width)
371 { return actualTC->readFloatReg(reg_idx, width); }
372
373 FloatReg readFloatReg(int reg_idx)
374 { return actualTC->readFloatReg(reg_idx); }
375
376 FloatRegBits readFloatRegBits(int reg_idx, int width)
377 { return actualTC->readFloatRegBits(reg_idx, width); }
378
379 FloatRegBits readFloatRegBits(int reg_idx)
380 { return actualTC->readFloatRegBits(reg_idx); }
381
382 void setIntReg(int reg_idx, uint64_t val)
383 { actualTC->setIntReg(reg_idx, val); }
384
385 void setFloatReg(int reg_idx, FloatReg val, int width)
386 { actualTC->setFloatReg(reg_idx, val, width); }
387
388 void setFloatReg(int reg_idx, FloatReg val)
389 { actualTC->setFloatReg(reg_idx, val); }
390
391 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
392 { actualTC->setFloatRegBits(reg_idx, val, width); }
393
394 void setFloatRegBits(int reg_idx, FloatRegBits val)
395 { actualTC->setFloatRegBits(reg_idx, val); }
396
397 uint64_t readPC() { return actualTC->readPC(); }
398
399 void setPC(uint64_t val) { actualTC->setPC(val); }
400
401 uint64_t readNextPC() { return actualTC->readNextPC(); }
402
403 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
404
405 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
406
407 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
408
409 MiscReg readMiscReg(int misc_reg)
410 { return actualTC->readMiscReg(misc_reg); }
411
412 MiscReg readMiscRegWithEffect(int misc_reg)
413 { return actualTC->readMiscRegWithEffect(misc_reg); }
414
415 void setMiscReg(int misc_reg, const MiscReg &val)
416 { return actualTC->setMiscReg(misc_reg, val); }
417
418 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
419 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
420
421 unsigned readStCondFailures()
422 { return actualTC->readStCondFailures(); }
423
424 void setStCondFailures(unsigned sc_failures)
425 { actualTC->setStCondFailures(sc_failures); }
426
427 // @todo: Fix this!
428 bool misspeculating() { return actualTC->misspeculating(); }
429
430#if !FULL_SYSTEM
431 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
432
433 // used to shift args for indirect syscall
434 void setSyscallArg(int i, IntReg val)
435 { actualTC->setSyscallArg(i, val); }
436
437 void setSyscallReturn(SyscallReturn return_value)
438 { actualTC->setSyscallReturn(return_value); }
439
440 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
441#endif
442
443 void changeRegFileContext(TheISA::RegContextParam param,
444 TheISA::RegContextVal val)
445 {
446 actualTC->changeRegFileContext(param, val);
447 }
448};
449
450#endif
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