1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/reg_class.hh"
55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60 class ISA;
61 class Decoder;
62}
63class BaseCPU;
64class BaseTLB;
65class CheckerCPU;
66class Checkpoint;
67class EndQuiesceEvent;
68class SETranslatingPortProxy;
69class FSTranslatingPortProxy;
70class PortProxy;
71class Process;
72class System;
| 1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/reg_class.hh"
55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60 class ISA;
61 class Decoder;
62}
63class BaseCPU;
64class BaseTLB;
65class CheckerCPU;
66class Checkpoint;
67class EndQuiesceEvent;
68class SETranslatingPortProxy;
69class FSTranslatingPortProxy;
70class PortProxy;
71class Process;
72class System;
|
73namespace TheISA {
74 namespace Kernel {
75 class Statistics;
76 }
| 73namespace Kernel {
74 class Statistics;
|
77}
78
79/**
80 * ThreadContext is the external interface to all thread state for
81 * anything outside of the CPU. It provides all accessor methods to
82 * state that might be needed by external objects, ranging from
83 * register values to things such as kernel stats. It is an abstract
84 * base class; the CPU can create its own ThreadContext by
85 * deriving from it.
86 *
87 * The ThreadContext is slightly different than the ExecContext. The
88 * ThreadContext provides access to an individual thread's state; an
89 * ExecContext provides ISA access to the CPU (meaning it is
90 * implicitly multithreaded on SMT systems). Additionally the
91 * ThreadState is an abstract class that exactly defines the
92 * interface; the ExecContext is a more implicit interface that must
93 * be implemented so that the ISA can access whatever state it needs.
94 */
95class ThreadContext
96{
97 protected:
98 typedef TheISA::MachInst MachInst;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
101 using VecPredRegContainer = TheISA::VecPredRegContainer;
102
103 public:
104
105 enum Status
106 {
107 /// Running. Instructions should be executed only when
108 /// the context is in this state.
109 Active,
110
111 /// Temporarily inactive. Entered while waiting for
112 /// synchronization, etc.
113 Suspended,
114
115 /// Trying to exit and waiting for an event to completely exit.
116 /// Entered when target executes an exit syscall.
117 Halting,
118
119 /// Permanently shut down. Entered when target executes
120 /// m5exit pseudo-instruction. When all contexts enter
121 /// this state, the simulation will terminate.
122 Halted
123 };
124
125 virtual ~ThreadContext() { };
126
127 virtual BaseCPU *getCpuPtr() = 0;
128
129 virtual int cpuId() const = 0;
130
131 virtual uint32_t socketId() const = 0;
132
133 virtual int threadId() const = 0;
134
135 virtual void setThreadId(int id) = 0;
136
137 virtual ContextID contextId() const = 0;
138
139 virtual void setContextId(ContextID id) = 0;
140
141 virtual BaseTLB *getITBPtr() = 0;
142
143 virtual BaseTLB *getDTBPtr() = 0;
144
145 virtual CheckerCPU *getCheckerCpuPtr() = 0;
146
147 virtual TheISA::ISA *getIsaPtr() = 0;
148
149 virtual TheISA::Decoder *getDecoderPtr() = 0;
150
151 virtual System *getSystemPtr() = 0;
152
| 75}
76
77/**
78 * ThreadContext is the external interface to all thread state for
79 * anything outside of the CPU. It provides all accessor methods to
80 * state that might be needed by external objects, ranging from
81 * register values to things such as kernel stats. It is an abstract
82 * base class; the CPU can create its own ThreadContext by
83 * deriving from it.
84 *
85 * The ThreadContext is slightly different than the ExecContext. The
86 * ThreadContext provides access to an individual thread's state; an
87 * ExecContext provides ISA access to the CPU (meaning it is
88 * implicitly multithreaded on SMT systems). Additionally the
89 * ThreadState is an abstract class that exactly defines the
90 * interface; the ExecContext is a more implicit interface that must
91 * be implemented so that the ISA can access whatever state it needs.
92 */
93class ThreadContext
94{
95 protected:
96 typedef TheISA::MachInst MachInst;
97 using VecRegContainer = TheISA::VecRegContainer;
98 using VecElem = TheISA::VecElem;
99 using VecPredRegContainer = TheISA::VecPredRegContainer;
100
101 public:
102
103 enum Status
104 {
105 /// Running. Instructions should be executed only when
106 /// the context is in this state.
107 Active,
108
109 /// Temporarily inactive. Entered while waiting for
110 /// synchronization, etc.
111 Suspended,
112
113 /// Trying to exit and waiting for an event to completely exit.
114 /// Entered when target executes an exit syscall.
115 Halting,
116
117 /// Permanently shut down. Entered when target executes
118 /// m5exit pseudo-instruction. When all contexts enter
119 /// this state, the simulation will terminate.
120 Halted
121 };
122
123 virtual ~ThreadContext() { };
124
125 virtual BaseCPU *getCpuPtr() = 0;
126
127 virtual int cpuId() const = 0;
128
129 virtual uint32_t socketId() const = 0;
130
131 virtual int threadId() const = 0;
132
133 virtual void setThreadId(int id) = 0;
134
135 virtual ContextID contextId() const = 0;
136
137 virtual void setContextId(ContextID id) = 0;
138
139 virtual BaseTLB *getITBPtr() = 0;
140
141 virtual BaseTLB *getDTBPtr() = 0;
142
143 virtual CheckerCPU *getCheckerCpuPtr() = 0;
144
145 virtual TheISA::ISA *getIsaPtr() = 0;
146
147 virtual TheISA::Decoder *getDecoderPtr() = 0;
148
149 virtual System *getSystemPtr() = 0;
150
|
153 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
| 151 virtual ::Kernel::Statistics *getKernelStats() = 0;
|
154
155 virtual PortProxy &getPhysProxy() = 0;
156
157 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
158
159 /**
160 * Initialise the physical and virtual port proxies and tie them to
161 * the data port of the CPU.
162 *
163 * tc ThreadContext for the virtual-to-physical translation
164 */
165 virtual void initMemProxies(ThreadContext *tc) = 0;
166
167 virtual SETranslatingPortProxy &getMemProxy() = 0;
168
169 virtual Process *getProcessPtr() = 0;
170
171 virtual void setProcessPtr(Process *p) = 0;
172
173 virtual Status status() const = 0;
174
175 virtual void setStatus(Status new_status) = 0;
176
177 /// Set the status to Active.
178 virtual void activate() = 0;
179
180 /// Set the status to Suspended.
181 virtual void suspend() = 0;
182
183 /// Set the status to Halted.
184 virtual void halt() = 0;
185
186 /// Quiesce thread context
187 void quiesce();
188
189 /// Quiesce, suspend, and schedule activate at resume
190 void quiesceTick(Tick resume);
191
192 virtual void dumpFuncProfile() = 0;
193
194 virtual void takeOverFrom(ThreadContext *old_context) = 0;
195
196 virtual void regStats(const std::string &name) = 0;
197
198 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
199
200 // Not necessarily the best location for these...
201 // Having an extra function just to read these is obnoxious
202 virtual Tick readLastActivate() = 0;
203 virtual Tick readLastSuspend() = 0;
204
205 virtual void profileClear() = 0;
206 virtual void profileSample() = 0;
207
208 virtual void copyArchRegs(ThreadContext *tc) = 0;
209
210 virtual void clearArchRegs() = 0;
211
212 //
213 // New accessors for new decoder.
214 //
215 virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
216
217 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
218
219 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
220 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
221
222 /** Vector Register Lane Interfaces. */
223 /** @{ */
224 /** Reads source vector 8bit operand. */
225 virtual ConstVecLane8
226 readVec8BitLaneReg(const RegId& reg) const = 0;
227
228 /** Reads source vector 16bit operand. */
229 virtual ConstVecLane16
230 readVec16BitLaneReg(const RegId& reg) const = 0;
231
232 /** Reads source vector 32bit operand. */
233 virtual ConstVecLane32
234 readVec32BitLaneReg(const RegId& reg) const = 0;
235
236 /** Reads source vector 64bit operand. */
237 virtual ConstVecLane64
238 readVec64BitLaneReg(const RegId& reg) const = 0;
239
240 /** Write a lane of the destination vector register. */
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::Byte>& val) = 0;
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::TwoByte>& val) = 0;
245 virtual void setVecLane(const RegId& reg,
246 const LaneData<LaneSize::FourByte>& val) = 0;
247 virtual void setVecLane(const RegId& reg,
248 const LaneData<LaneSize::EightByte>& val) = 0;
249 /** @} */
250
251 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
252
253 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
254 const = 0;
255 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
256
257 virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
258
259 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
260
261 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
262
263 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
264
265 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
266
267 virtual void setVecPredReg(const RegId& reg,
268 const VecPredRegContainer& val) = 0;
269
270 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
271
272 virtual TheISA::PCState pcState() const = 0;
273
274 virtual void pcState(const TheISA::PCState &val) = 0;
275
276 void
277 setNPC(Addr val)
278 {
279 TheISA::PCState pc_state = pcState();
280 pc_state.setNPC(val);
281 pcState(pc_state);
282 }
283
284 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
285
286 virtual Addr instAddr() const = 0;
287
288 virtual Addr nextInstAddr() const = 0;
289
290 virtual MicroPC microPC() const = 0;
291
292 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
293
294 virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
295
296 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
297
298 virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
299
300 virtual RegId flattenRegId(const RegId& regId) const = 0;
301
302 // Also not necessarily the best location for these two. Hopefully will go
303 // away once we decide upon where st cond failures goes.
304 virtual unsigned readStCondFailures() const = 0;
305
306 virtual void setStCondFailures(unsigned sc_failures) = 0;
307
308 // Same with st cond failures.
309 virtual Counter readFuncExeInst() const = 0;
310
311 virtual void syscall(int64_t callnum, Fault *fault) = 0;
312
313 // This function exits the thread context in the CPU and returns
314 // 1 if the CPU has no more active threads (meaning it's OK to exit);
315 // Used in syscall-emulation mode when a thread calls the exit syscall.
316 virtual int exit() { return 1; };
317
318 /** function to compare two thread contexts (for debugging) */
319 static void compare(ThreadContext *one, ThreadContext *two);
320
321 /** @{ */
322 /**
323 * Flat register interfaces
324 *
325 * Some architectures have different registers visible in
326 * different modes. Such architectures "flatten" a register (see
327 * flattenRegId()) to map it into the
328 * gem5 register file. This interface provides a flat interface to
329 * the underlying register file, which allows for example
330 * serialization code to access all registers.
331 */
332
333 virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
334 virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
335
336 virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
337 virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
338
339 virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
340 virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
341 virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
342
343 virtual const VecElem& readVecElemFlat(RegIndex idx,
344 const ElemIndex& elemIdx) const = 0;
345 virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
346 const VecElem& val) = 0;
347
348 virtual const VecPredRegContainer &
349 readVecPredRegFlat(RegIndex idx) const = 0;
350 virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
351 virtual void setVecPredRegFlat(RegIndex idx,
352 const VecPredRegContainer& val) = 0;
353
354 virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
355 virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
356 /** @} */
357
358};
359
360/** @{ */
361/**
362 * Thread context serialization helpers
363 *
364 * These helper functions provide a way to the data in a
365 * ThreadContext. They are provided as separate helper function since
366 * implementing them as members of the ThreadContext interface would
367 * be confusing when the ThreadContext is exported via a proxy.
368 */
369
370void serialize(const ThreadContext &tc, CheckpointOut &cp);
371void unserialize(ThreadContext &tc, CheckpointIn &cp);
372
373/** @} */
374
375
376/**
377 * Copy state between thread contexts in preparation for CPU handover.
378 *
379 * @note This method modifies the old thread contexts as well as the
380 * new thread context. The old thread context will have its quiesce
381 * event descheduled if it is scheduled and its status set to halted.
382 *
383 * @param new_tc Destination ThreadContext.
384 * @param old_tc Source ThreadContext.
385 */
386void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
387
388#endif
| 152
153 virtual PortProxy &getPhysProxy() = 0;
154
155 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
156
157 /**
158 * Initialise the physical and virtual port proxies and tie them to
159 * the data port of the CPU.
160 *
161 * tc ThreadContext for the virtual-to-physical translation
162 */
163 virtual void initMemProxies(ThreadContext *tc) = 0;
164
165 virtual SETranslatingPortProxy &getMemProxy() = 0;
166
167 virtual Process *getProcessPtr() = 0;
168
169 virtual void setProcessPtr(Process *p) = 0;
170
171 virtual Status status() const = 0;
172
173 virtual void setStatus(Status new_status) = 0;
174
175 /// Set the status to Active.
176 virtual void activate() = 0;
177
178 /// Set the status to Suspended.
179 virtual void suspend() = 0;
180
181 /// Set the status to Halted.
182 virtual void halt() = 0;
183
184 /// Quiesce thread context
185 void quiesce();
186
187 /// Quiesce, suspend, and schedule activate at resume
188 void quiesceTick(Tick resume);
189
190 virtual void dumpFuncProfile() = 0;
191
192 virtual void takeOverFrom(ThreadContext *old_context) = 0;
193
194 virtual void regStats(const std::string &name) = 0;
195
196 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
197
198 // Not necessarily the best location for these...
199 // Having an extra function just to read these is obnoxious
200 virtual Tick readLastActivate() = 0;
201 virtual Tick readLastSuspend() = 0;
202
203 virtual void profileClear() = 0;
204 virtual void profileSample() = 0;
205
206 virtual void copyArchRegs(ThreadContext *tc) = 0;
207
208 virtual void clearArchRegs() = 0;
209
210 //
211 // New accessors for new decoder.
212 //
213 virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
214
215 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
216
217 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
218 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
219
220 /** Vector Register Lane Interfaces. */
221 /** @{ */
222 /** Reads source vector 8bit operand. */
223 virtual ConstVecLane8
224 readVec8BitLaneReg(const RegId& reg) const = 0;
225
226 /** Reads source vector 16bit operand. */
227 virtual ConstVecLane16
228 readVec16BitLaneReg(const RegId& reg) const = 0;
229
230 /** Reads source vector 32bit operand. */
231 virtual ConstVecLane32
232 readVec32BitLaneReg(const RegId& reg) const = 0;
233
234 /** Reads source vector 64bit operand. */
235 virtual ConstVecLane64
236 readVec64BitLaneReg(const RegId& reg) const = 0;
237
238 /** Write a lane of the destination vector register. */
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::Byte>& val) = 0;
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::TwoByte>& val) = 0;
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::FourByte>& val) = 0;
245 virtual void setVecLane(const RegId& reg,
246 const LaneData<LaneSize::EightByte>& val) = 0;
247 /** @} */
248
249 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
250
251 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
252 const = 0;
253 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
254
255 virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
256
257 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
258
259 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
260
261 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
262
263 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
264
265 virtual void setVecPredReg(const RegId& reg,
266 const VecPredRegContainer& val) = 0;
267
268 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
269
270 virtual TheISA::PCState pcState() const = 0;
271
272 virtual void pcState(const TheISA::PCState &val) = 0;
273
274 void
275 setNPC(Addr val)
276 {
277 TheISA::PCState pc_state = pcState();
278 pc_state.setNPC(val);
279 pcState(pc_state);
280 }
281
282 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
283
284 virtual Addr instAddr() const = 0;
285
286 virtual Addr nextInstAddr() const = 0;
287
288 virtual MicroPC microPC() const = 0;
289
290 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
291
292 virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
293
294 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
295
296 virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
297
298 virtual RegId flattenRegId(const RegId& regId) const = 0;
299
300 // Also not necessarily the best location for these two. Hopefully will go
301 // away once we decide upon where st cond failures goes.
302 virtual unsigned readStCondFailures() const = 0;
303
304 virtual void setStCondFailures(unsigned sc_failures) = 0;
305
306 // Same with st cond failures.
307 virtual Counter readFuncExeInst() const = 0;
308
309 virtual void syscall(int64_t callnum, Fault *fault) = 0;
310
311 // This function exits the thread context in the CPU and returns
312 // 1 if the CPU has no more active threads (meaning it's OK to exit);
313 // Used in syscall-emulation mode when a thread calls the exit syscall.
314 virtual int exit() { return 1; };
315
316 /** function to compare two thread contexts (for debugging) */
317 static void compare(ThreadContext *one, ThreadContext *two);
318
319 /** @{ */
320 /**
321 * Flat register interfaces
322 *
323 * Some architectures have different registers visible in
324 * different modes. Such architectures "flatten" a register (see
325 * flattenRegId()) to map it into the
326 * gem5 register file. This interface provides a flat interface to
327 * the underlying register file, which allows for example
328 * serialization code to access all registers.
329 */
330
331 virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
332 virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
333
334 virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
335 virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
336
337 virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
338 virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
339 virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
340
341 virtual const VecElem& readVecElemFlat(RegIndex idx,
342 const ElemIndex& elemIdx) const = 0;
343 virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
344 const VecElem& val) = 0;
345
346 virtual const VecPredRegContainer &
347 readVecPredRegFlat(RegIndex idx) const = 0;
348 virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
349 virtual void setVecPredRegFlat(RegIndex idx,
350 const VecPredRegContainer& val) = 0;
351
352 virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
353 virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
354 /** @} */
355
356};
357
358/** @{ */
359/**
360 * Thread context serialization helpers
361 *
362 * These helper functions provide a way to the data in a
363 * ThreadContext. They are provided as separate helper function since
364 * implementing them as members of the ThreadContext interface would
365 * be confusing when the ThreadContext is exported via a proxy.
366 */
367
368void serialize(const ThreadContext &tc, CheckpointOut &cp);
369void unserialize(ThreadContext &tc, CheckpointIn &cp);
370
371/** @} */
372
373
374/**
375 * Copy state between thread contexts in preparation for CPU handover.
376 *
377 * @note This method modifies the old thread contexts as well as the
378 * new thread context. The old thread context will have its quiesce
379 * event descheduled if it is scheduled and its status set to halted.
380 *
381 * @param new_tc Destination ThreadContext.
382 * @param old_tc Source ThreadContext.
383 */
384void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
385
386#endif
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