1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/reg_class.hh"
55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60 class Decoder;
| 1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/reg_class.hh"
55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60 class Decoder;
|
61 class TLB;
| |
62}
63class BaseCPU;
| 61}
62class BaseCPU;
|
| 63class BaseTLB;
|
64class CheckerCPU;
65class Checkpoint;
66class EndQuiesceEvent;
67class SETranslatingPortProxy;
68class FSTranslatingPortProxy;
69class PortProxy;
70class Process;
71class System;
72namespace TheISA {
73 namespace Kernel {
74 class Statistics;
75 }
76}
77
78/**
79 * ThreadContext is the external interface to all thread state for
80 * anything outside of the CPU. It provides all accessor methods to
81 * state that might be needed by external objects, ranging from
82 * register values to things such as kernel stats. It is an abstract
83 * base class; the CPU can create its own ThreadContext by either
84 * deriving from it, or using the templated ProxyThreadContext.
85 *
86 * The ThreadContext is slightly different than the ExecContext. The
87 * ThreadContext provides access to an individual thread's state; an
88 * ExecContext provides ISA access to the CPU (meaning it is
89 * implicitly multithreaded on SMT systems). Additionally the
90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::IntReg IntReg;
99 typedef TheISA::FloatReg FloatReg;
100 typedef TheISA::FloatRegBits FloatRegBits;
101 typedef TheISA::CCReg CCReg;
102 typedef TheISA::MiscReg MiscReg;
103 using VecRegContainer = TheISA::VecRegContainer;
104 using VecElem = TheISA::VecElem;
105 public:
106
107 enum Status
108 {
109 /// Running. Instructions should be executed only when
110 /// the context is in this state.
111 Active,
112
113 /// Temporarily inactive. Entered while waiting for
114 /// synchronization, etc.
115 Suspended,
116
117 /// Permanently shut down. Entered when target executes
118 /// m5exit pseudo-instruction. When all contexts enter
119 /// this state, the simulation will terminate.
120 Halted
121 };
122
123 virtual ~ThreadContext() { };
124
125 virtual BaseCPU *getCpuPtr() = 0;
126
127 virtual int cpuId() const = 0;
128
129 virtual uint32_t socketId() const = 0;
130
131 virtual int threadId() const = 0;
132
133 virtual void setThreadId(int id) = 0;
134
135 virtual int contextId() const = 0;
136
137 virtual void setContextId(int id) = 0;
138
| 64class CheckerCPU;
65class Checkpoint;
66class EndQuiesceEvent;
67class SETranslatingPortProxy;
68class FSTranslatingPortProxy;
69class PortProxy;
70class Process;
71class System;
72namespace TheISA {
73 namespace Kernel {
74 class Statistics;
75 }
76}
77
78/**
79 * ThreadContext is the external interface to all thread state for
80 * anything outside of the CPU. It provides all accessor methods to
81 * state that might be needed by external objects, ranging from
82 * register values to things such as kernel stats. It is an abstract
83 * base class; the CPU can create its own ThreadContext by either
84 * deriving from it, or using the templated ProxyThreadContext.
85 *
86 * The ThreadContext is slightly different than the ExecContext. The
87 * ThreadContext provides access to an individual thread's state; an
88 * ExecContext provides ISA access to the CPU (meaning it is
89 * implicitly multithreaded on SMT systems). Additionally the
90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::IntReg IntReg;
99 typedef TheISA::FloatReg FloatReg;
100 typedef TheISA::FloatRegBits FloatRegBits;
101 typedef TheISA::CCReg CCReg;
102 typedef TheISA::MiscReg MiscReg;
103 using VecRegContainer = TheISA::VecRegContainer;
104 using VecElem = TheISA::VecElem;
105 public:
106
107 enum Status
108 {
109 /// Running. Instructions should be executed only when
110 /// the context is in this state.
111 Active,
112
113 /// Temporarily inactive. Entered while waiting for
114 /// synchronization, etc.
115 Suspended,
116
117 /// Permanently shut down. Entered when target executes
118 /// m5exit pseudo-instruction. When all contexts enter
119 /// this state, the simulation will terminate.
120 Halted
121 };
122
123 virtual ~ThreadContext() { };
124
125 virtual BaseCPU *getCpuPtr() = 0;
126
127 virtual int cpuId() const = 0;
128
129 virtual uint32_t socketId() const = 0;
130
131 virtual int threadId() const = 0;
132
133 virtual void setThreadId(int id) = 0;
134
135 virtual int contextId() const = 0;
136
137 virtual void setContextId(int id) = 0;
138
|
139 virtual TheISA::TLB *getITBPtr() = 0;
| 139 virtual BaseTLB *getITBPtr() = 0;
|
140
| 140
|
141 virtual TheISA::TLB *getDTBPtr() = 0;
| 141 virtual BaseTLB *getDTBPtr() = 0;
|
142
143 virtual CheckerCPU *getCheckerCpuPtr() = 0;
144
145 virtual TheISA::Decoder *getDecoderPtr() = 0;
146
147 virtual System *getSystemPtr() = 0;
148
149 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
150
151 virtual PortProxy &getPhysProxy() = 0;
152
153 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
154
155 /**
156 * Initialise the physical and virtual port proxies and tie them to
157 * the data port of the CPU.
158 *
159 * tc ThreadContext for the virtual-to-physical translation
160 */
161 virtual void initMemProxies(ThreadContext *tc) = 0;
162
163 virtual SETranslatingPortProxy &getMemProxy() = 0;
164
165 virtual Process *getProcessPtr() = 0;
166
167 virtual void setProcessPtr(Process *p) = 0;
168
169 virtual Status status() const = 0;
170
171 virtual void setStatus(Status new_status) = 0;
172
173 /// Set the status to Active.
174 virtual void activate() = 0;
175
176 /// Set the status to Suspended.
177 virtual void suspend() = 0;
178
179 /// Set the status to Halted.
180 virtual void halt() = 0;
181
182 /// Quiesce thread context
183 void quiesce();
184
185 /// Quiesce, suspend, and schedule activate at resume
186 void quiesceTick(Tick resume);
187
188 virtual void dumpFuncProfile() = 0;
189
190 virtual void takeOverFrom(ThreadContext *old_context) = 0;
191
192 virtual void regStats(const std::string &name) = 0;
193
194 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
195
196 // Not necessarily the best location for these...
197 // Having an extra function just to read these is obnoxious
198 virtual Tick readLastActivate() = 0;
199 virtual Tick readLastSuspend() = 0;
200
201 virtual void profileClear() = 0;
202 virtual void profileSample() = 0;
203
204 virtual void copyArchRegs(ThreadContext *tc) = 0;
205
206 virtual void clearArchRegs() = 0;
207
208 //
209 // New accessors for new decoder.
210 //
211 virtual uint64_t readIntReg(int reg_idx) = 0;
212
213 virtual FloatReg readFloatReg(int reg_idx) = 0;
214
215 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
216
217 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
218 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
219
220 /** Vector Register Lane Interfaces. */
221 /** @{ */
222 /** Reads source vector 8bit operand. */
223 virtual ConstVecLane8
224 readVec8BitLaneReg(const RegId& reg) const = 0;
225
226 /** Reads source vector 16bit operand. */
227 virtual ConstVecLane16
228 readVec16BitLaneReg(const RegId& reg) const = 0;
229
230 /** Reads source vector 32bit operand. */
231 virtual ConstVecLane32
232 readVec32BitLaneReg(const RegId& reg) const = 0;
233
234 /** Reads source vector 64bit operand. */
235 virtual ConstVecLane64
236 readVec64BitLaneReg(const RegId& reg) const = 0;
237
238 /** Write a lane of the destination vector register. */
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::Byte>& val) = 0;
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::TwoByte>& val) = 0;
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::FourByte>& val) = 0;
245 virtual void setVecLane(const RegId& reg,
246 const LaneData<LaneSize::EightByte>& val) = 0;
247 /** @} */
248
249 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
250
251 virtual CCReg readCCReg(int reg_idx) = 0;
252
253 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
254
255 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
256
257 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
258
259 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
260
261 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
262
263 virtual void setCCReg(int reg_idx, CCReg val) = 0;
264
265 virtual TheISA::PCState pcState() = 0;
266
267 virtual void pcState(const TheISA::PCState &val) = 0;
268
269 void
270 setNPC(Addr val)
271 {
272 TheISA::PCState pc_state = pcState();
273 pc_state.setNPC(val);
274 pcState(pc_state);
275 }
276
277 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
278
279 virtual Addr instAddr() = 0;
280
281 virtual Addr nextInstAddr() = 0;
282
283 virtual MicroPC microPC() = 0;
284
285 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
286
287 virtual MiscReg readMiscReg(int misc_reg) = 0;
288
289 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
290
291 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
292
293 virtual RegId flattenRegId(const RegId& regId) const = 0;
294
295 virtual uint64_t
296 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
297 {
298 return 0;
299 }
300
301 virtual void
302 setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid)
303 {
304 }
305
306 // Also not necessarily the best location for these two. Hopefully will go
307 // away once we decide upon where st cond failures goes.
308 virtual unsigned readStCondFailures() = 0;
309
310 virtual void setStCondFailures(unsigned sc_failures) = 0;
311
312 // Same with st cond failures.
313 virtual Counter readFuncExeInst() = 0;
314
315 virtual void syscall(int64_t callnum, Fault *fault) = 0;
316
317 // This function exits the thread context in the CPU and returns
318 // 1 if the CPU has no more active threads (meaning it's OK to exit);
319 // Used in syscall-emulation mode when a thread calls the exit syscall.
320 virtual int exit() { return 1; };
321
322 /** function to compare two thread contexts (for debugging) */
323 static void compare(ThreadContext *one, ThreadContext *two);
324
325 /** @{ */
326 /**
327 * Flat register interfaces
328 *
329 * Some architectures have different registers visible in
330 * different modes. Such architectures "flatten" a register (see
331 * flattenRegId()) to map it into the
332 * gem5 register file. This interface provides a flat interface to
333 * the underlying register file, which allows for example
334 * serialization code to access all registers.
335 */
336
337 virtual uint64_t readIntRegFlat(int idx) = 0;
338 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
339
340 virtual FloatReg readFloatRegFlat(int idx) = 0;
341 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
342
343 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
344 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
345
346 virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
347 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
348 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
349
350 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
351 const ElemIndex& elemIdx) const = 0;
352 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
353 const VecElem& val) = 0;
354
355 virtual CCReg readCCRegFlat(int idx) = 0;
356 virtual void setCCRegFlat(int idx, CCReg val) = 0;
357 /** @} */
358
359};
360
361/**
362 * ProxyThreadContext class that provides a way to implement a
363 * ThreadContext without having to derive from it. ThreadContext is an
364 * abstract class, so anything that derives from it and uses its
365 * interface will pay the overhead of virtual function calls. This
366 * class is created to enable a user-defined Thread object to be used
367 * wherever ThreadContexts are used, without paying the overhead of
368 * virtual function calls when it is used by itself. See
369 * simple_thread.hh for an example of this.
370 */
371template <class TC>
372class ProxyThreadContext : public ThreadContext
373{
374 public:
375 ProxyThreadContext(TC *actual_tc)
376 { actualTC = actual_tc; }
377
378 private:
379 TC *actualTC;
380
381 public:
382
383 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
384
385 int cpuId() const { return actualTC->cpuId(); }
386
387 uint32_t socketId() const { return actualTC->socketId(); }
388
389 int threadId() const { return actualTC->threadId(); }
390
391 void setThreadId(int id) { actualTC->setThreadId(id); }
392
393 int contextId() const { return actualTC->contextId(); }
394
395 void setContextId(int id) { actualTC->setContextId(id); }
396
| 142
143 virtual CheckerCPU *getCheckerCpuPtr() = 0;
144
145 virtual TheISA::Decoder *getDecoderPtr() = 0;
146
147 virtual System *getSystemPtr() = 0;
148
149 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
150
151 virtual PortProxy &getPhysProxy() = 0;
152
153 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
154
155 /**
156 * Initialise the physical and virtual port proxies and tie them to
157 * the data port of the CPU.
158 *
159 * tc ThreadContext for the virtual-to-physical translation
160 */
161 virtual void initMemProxies(ThreadContext *tc) = 0;
162
163 virtual SETranslatingPortProxy &getMemProxy() = 0;
164
165 virtual Process *getProcessPtr() = 0;
166
167 virtual void setProcessPtr(Process *p) = 0;
168
169 virtual Status status() const = 0;
170
171 virtual void setStatus(Status new_status) = 0;
172
173 /// Set the status to Active.
174 virtual void activate() = 0;
175
176 /// Set the status to Suspended.
177 virtual void suspend() = 0;
178
179 /// Set the status to Halted.
180 virtual void halt() = 0;
181
182 /// Quiesce thread context
183 void quiesce();
184
185 /// Quiesce, suspend, and schedule activate at resume
186 void quiesceTick(Tick resume);
187
188 virtual void dumpFuncProfile() = 0;
189
190 virtual void takeOverFrom(ThreadContext *old_context) = 0;
191
192 virtual void regStats(const std::string &name) = 0;
193
194 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
195
196 // Not necessarily the best location for these...
197 // Having an extra function just to read these is obnoxious
198 virtual Tick readLastActivate() = 0;
199 virtual Tick readLastSuspend() = 0;
200
201 virtual void profileClear() = 0;
202 virtual void profileSample() = 0;
203
204 virtual void copyArchRegs(ThreadContext *tc) = 0;
205
206 virtual void clearArchRegs() = 0;
207
208 //
209 // New accessors for new decoder.
210 //
211 virtual uint64_t readIntReg(int reg_idx) = 0;
212
213 virtual FloatReg readFloatReg(int reg_idx) = 0;
214
215 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
216
217 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
218 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
219
220 /** Vector Register Lane Interfaces. */
221 /** @{ */
222 /** Reads source vector 8bit operand. */
223 virtual ConstVecLane8
224 readVec8BitLaneReg(const RegId& reg) const = 0;
225
226 /** Reads source vector 16bit operand. */
227 virtual ConstVecLane16
228 readVec16BitLaneReg(const RegId& reg) const = 0;
229
230 /** Reads source vector 32bit operand. */
231 virtual ConstVecLane32
232 readVec32BitLaneReg(const RegId& reg) const = 0;
233
234 /** Reads source vector 64bit operand. */
235 virtual ConstVecLane64
236 readVec64BitLaneReg(const RegId& reg) const = 0;
237
238 /** Write a lane of the destination vector register. */
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::Byte>& val) = 0;
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::TwoByte>& val) = 0;
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::FourByte>& val) = 0;
245 virtual void setVecLane(const RegId& reg,
246 const LaneData<LaneSize::EightByte>& val) = 0;
247 /** @} */
248
249 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
250
251 virtual CCReg readCCReg(int reg_idx) = 0;
252
253 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
254
255 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
256
257 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
258
259 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
260
261 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
262
263 virtual void setCCReg(int reg_idx, CCReg val) = 0;
264
265 virtual TheISA::PCState pcState() = 0;
266
267 virtual void pcState(const TheISA::PCState &val) = 0;
268
269 void
270 setNPC(Addr val)
271 {
272 TheISA::PCState pc_state = pcState();
273 pc_state.setNPC(val);
274 pcState(pc_state);
275 }
276
277 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
278
279 virtual Addr instAddr() = 0;
280
281 virtual Addr nextInstAddr() = 0;
282
283 virtual MicroPC microPC() = 0;
284
285 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
286
287 virtual MiscReg readMiscReg(int misc_reg) = 0;
288
289 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
290
291 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
292
293 virtual RegId flattenRegId(const RegId& regId) const = 0;
294
295 virtual uint64_t
296 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
297 {
298 return 0;
299 }
300
301 virtual void
302 setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid)
303 {
304 }
305
306 // Also not necessarily the best location for these two. Hopefully will go
307 // away once we decide upon where st cond failures goes.
308 virtual unsigned readStCondFailures() = 0;
309
310 virtual void setStCondFailures(unsigned sc_failures) = 0;
311
312 // Same with st cond failures.
313 virtual Counter readFuncExeInst() = 0;
314
315 virtual void syscall(int64_t callnum, Fault *fault) = 0;
316
317 // This function exits the thread context in the CPU and returns
318 // 1 if the CPU has no more active threads (meaning it's OK to exit);
319 // Used in syscall-emulation mode when a thread calls the exit syscall.
320 virtual int exit() { return 1; };
321
322 /** function to compare two thread contexts (for debugging) */
323 static void compare(ThreadContext *one, ThreadContext *two);
324
325 /** @{ */
326 /**
327 * Flat register interfaces
328 *
329 * Some architectures have different registers visible in
330 * different modes. Such architectures "flatten" a register (see
331 * flattenRegId()) to map it into the
332 * gem5 register file. This interface provides a flat interface to
333 * the underlying register file, which allows for example
334 * serialization code to access all registers.
335 */
336
337 virtual uint64_t readIntRegFlat(int idx) = 0;
338 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
339
340 virtual FloatReg readFloatRegFlat(int idx) = 0;
341 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
342
343 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
344 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
345
346 virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
347 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
348 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
349
350 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
351 const ElemIndex& elemIdx) const = 0;
352 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
353 const VecElem& val) = 0;
354
355 virtual CCReg readCCRegFlat(int idx) = 0;
356 virtual void setCCRegFlat(int idx, CCReg val) = 0;
357 /** @} */
358
359};
360
361/**
362 * ProxyThreadContext class that provides a way to implement a
363 * ThreadContext without having to derive from it. ThreadContext is an
364 * abstract class, so anything that derives from it and uses its
365 * interface will pay the overhead of virtual function calls. This
366 * class is created to enable a user-defined Thread object to be used
367 * wherever ThreadContexts are used, without paying the overhead of
368 * virtual function calls when it is used by itself. See
369 * simple_thread.hh for an example of this.
370 */
371template <class TC>
372class ProxyThreadContext : public ThreadContext
373{
374 public:
375 ProxyThreadContext(TC *actual_tc)
376 { actualTC = actual_tc; }
377
378 private:
379 TC *actualTC;
380
381 public:
382
383 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
384
385 int cpuId() const { return actualTC->cpuId(); }
386
387 uint32_t socketId() const { return actualTC->socketId(); }
388
389 int threadId() const { return actualTC->threadId(); }
390
391 void setThreadId(int id) { actualTC->setThreadId(id); }
392
393 int contextId() const { return actualTC->contextId(); }
394
395 void setContextId(int id) { actualTC->setContextId(id); }
396
|
397 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
| 397 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
|
398
| 398
|
399 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
| 399 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
|
400
401 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
402
403 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
404
405 System *getSystemPtr() { return actualTC->getSystemPtr(); }
406
407 TheISA::Kernel::Statistics *getKernelStats()
408 { return actualTC->getKernelStats(); }
409
410 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
411
412 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
413
414 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
415
416 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
417
418 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
419
420 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
421
422 Status status() const { return actualTC->status(); }
423
424 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
425
426 /// Set the status to Active.
427 void activate() { actualTC->activate(); }
428
429 /// Set the status to Suspended.
430 void suspend() { actualTC->suspend(); }
431
432 /// Set the status to Halted.
433 void halt() { actualTC->halt(); }
434
435 /// Quiesce thread context
436 void quiesce() { actualTC->quiesce(); }
437
438 /// Quiesce, suspend, and schedule activate at resume
439 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
440
441 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
442
443 void takeOverFrom(ThreadContext *oldContext)
444 { actualTC->takeOverFrom(oldContext); }
445
446 void regStats(const std::string &name) { actualTC->regStats(name); }
447
448 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
449
450 Tick readLastActivate() { return actualTC->readLastActivate(); }
451 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
452
453 void profileClear() { return actualTC->profileClear(); }
454 void profileSample() { return actualTC->profileSample(); }
455
456 // @todo: Do I need this?
457 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
458
459 void clearArchRegs() { actualTC->clearArchRegs(); }
460
461 //
462 // New accessors for new decoder.
463 //
464 uint64_t readIntReg(int reg_idx)
465 { return actualTC->readIntReg(reg_idx); }
466
467 FloatReg readFloatReg(int reg_idx)
468 { return actualTC->readFloatReg(reg_idx); }
469
470 FloatRegBits readFloatRegBits(int reg_idx)
471 { return actualTC->readFloatRegBits(reg_idx); }
472
473 const VecRegContainer& readVecReg(const RegId& reg) const
474 { return actualTC->readVecReg(reg); }
475
476 VecRegContainer& getWritableVecReg(const RegId& reg)
477 { return actualTC->getWritableVecReg(reg); }
478
479 /** Vector Register Lane Interfaces. */
480 /** @{ */
481 /** Reads source vector 8bit operand. */
482 ConstVecLane8
483 readVec8BitLaneReg(const RegId& reg) const
484 { return actualTC->readVec8BitLaneReg(reg); }
485
486 /** Reads source vector 16bit operand. */
487 ConstVecLane16
488 readVec16BitLaneReg(const RegId& reg) const
489 { return actualTC->readVec16BitLaneReg(reg); }
490
491 /** Reads source vector 32bit operand. */
492 ConstVecLane32
493 readVec32BitLaneReg(const RegId& reg) const
494 { return actualTC->readVec32BitLaneReg(reg); }
495
496 /** Reads source vector 64bit operand. */
497 ConstVecLane64
498 readVec64BitLaneReg(const RegId& reg) const
499 { return actualTC->readVec64BitLaneReg(reg); }
500
501 /** Write a lane of the destination vector register. */
502 virtual void setVecLane(const RegId& reg,
503 const LaneData<LaneSize::Byte>& val)
504 { return actualTC->setVecLane(reg, val); }
505 virtual void setVecLane(const RegId& reg,
506 const LaneData<LaneSize::TwoByte>& val)
507 { return actualTC->setVecLane(reg, val); }
508 virtual void setVecLane(const RegId& reg,
509 const LaneData<LaneSize::FourByte>& val)
510 { return actualTC->setVecLane(reg, val); }
511 virtual void setVecLane(const RegId& reg,
512 const LaneData<LaneSize::EightByte>& val)
513 { return actualTC->setVecLane(reg, val); }
514 /** @} */
515
516 const VecElem& readVecElem(const RegId& reg) const
517 { return actualTC->readVecElem(reg); }
518
519 CCReg readCCReg(int reg_idx)
520 { return actualTC->readCCReg(reg_idx); }
521
522 void setIntReg(int reg_idx, uint64_t val)
523 { actualTC->setIntReg(reg_idx, val); }
524
525 void setFloatReg(int reg_idx, FloatReg val)
526 { actualTC->setFloatReg(reg_idx, val); }
527
528 void setFloatRegBits(int reg_idx, FloatRegBits val)
529 { actualTC->setFloatRegBits(reg_idx, val); }
530
531 void setVecReg(const RegId& reg, const VecRegContainer& val)
532 { actualTC->setVecReg(reg, val); }
533
534 void setVecElem(const RegId& reg, const VecElem& val)
535 { actualTC->setVecElem(reg, val); }
536
537 void setCCReg(int reg_idx, CCReg val)
538 { actualTC->setCCReg(reg_idx, val); }
539
540 TheISA::PCState pcState() { return actualTC->pcState(); }
541
542 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
543
544 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
545
546 Addr instAddr() { return actualTC->instAddr(); }
547 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
548 MicroPC microPC() { return actualTC->microPC(); }
549
550 bool readPredicate() { return actualTC->readPredicate(); }
551
552 void setPredicate(bool val)
553 { actualTC->setPredicate(val); }
554
555 MiscReg readMiscRegNoEffect(int misc_reg) const
556 { return actualTC->readMiscRegNoEffect(misc_reg); }
557
558 MiscReg readMiscReg(int misc_reg)
559 { return actualTC->readMiscReg(misc_reg); }
560
561 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
562 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
563
564 void setMiscReg(int misc_reg, const MiscReg &val)
565 { return actualTC->setMiscReg(misc_reg, val); }
566
567 RegId flattenRegId(const RegId& regId) const
568 { return actualTC->flattenRegId(regId); }
569
570 unsigned readStCondFailures()
571 { return actualTC->readStCondFailures(); }
572
573 void setStCondFailures(unsigned sc_failures)
574 { actualTC->setStCondFailures(sc_failures); }
575
576 void syscall(int64_t callnum, Fault *fault)
577 { actualTC->syscall(callnum, fault); }
578
579 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
580
581 uint64_t readIntRegFlat(int idx)
582 { return actualTC->readIntRegFlat(idx); }
583
584 void setIntRegFlat(int idx, uint64_t val)
585 { actualTC->setIntRegFlat(idx, val); }
586
587 FloatReg readFloatRegFlat(int idx)
588 { return actualTC->readFloatRegFlat(idx); }
589
590 void setFloatRegFlat(int idx, FloatReg val)
591 { actualTC->setFloatRegFlat(idx, val); }
592
593 FloatRegBits readFloatRegBitsFlat(int idx)
594 { return actualTC->readFloatRegBitsFlat(idx); }
595
596 void setFloatRegBitsFlat(int idx, FloatRegBits val)
597 { actualTC->setFloatRegBitsFlat(idx, val); }
598
599 const VecRegContainer& readVecRegFlat(int id) const
600 { return actualTC->readVecRegFlat(id); }
601
602 VecRegContainer& getWritableVecRegFlat(int id)
603 { return actualTC->getWritableVecRegFlat(id); }
604
605 void setVecRegFlat(int idx, const VecRegContainer& val)
606 { actualTC->setVecRegFlat(idx, val); }
607
608 const VecElem& readVecElemFlat(const RegIndex& id,
609 const ElemIndex& elemIndex) const
610 { return actualTC->readVecElemFlat(id, elemIndex); }
611
612 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
613 const VecElem& val)
614 { actualTC->setVecElemFlat(id, elemIndex, val); }
615
616 CCReg readCCRegFlat(int idx)
617 { return actualTC->readCCRegFlat(idx); }
618
619 void setCCRegFlat(int idx, CCReg val)
620 { actualTC->setCCRegFlat(idx, val); }
621};
622
623/** @{ */
624/**
625 * Thread context serialization helpers
626 *
627 * These helper functions provide a way to the data in a
628 * ThreadContext. They are provided as separate helper function since
629 * implementing them as members of the ThreadContext interface would
630 * be confusing when the ThreadContext is exported via a proxy.
631 */
632
633void serialize(ThreadContext &tc, CheckpointOut &cp);
634void unserialize(ThreadContext &tc, CheckpointIn &cp);
635
636/** @} */
637
638
639/**
640 * Copy state between thread contexts in preparation for CPU handover.
641 *
642 * @note This method modifies the old thread contexts as well as the
643 * new thread context. The old thread context will have its quiesce
644 * event descheduled if it is scheduled and its status set to halted.
645 *
646 * @param new_tc Destination ThreadContext.
647 * @param old_tc Source ThreadContext.
648 */
649void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
650
651#endif
| 400
401 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
402
403 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
404
405 System *getSystemPtr() { return actualTC->getSystemPtr(); }
406
407 TheISA::Kernel::Statistics *getKernelStats()
408 { return actualTC->getKernelStats(); }
409
410 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
411
412 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
413
414 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
415
416 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
417
418 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
419
420 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
421
422 Status status() const { return actualTC->status(); }
423
424 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
425
426 /// Set the status to Active.
427 void activate() { actualTC->activate(); }
428
429 /// Set the status to Suspended.
430 void suspend() { actualTC->suspend(); }
431
432 /// Set the status to Halted.
433 void halt() { actualTC->halt(); }
434
435 /// Quiesce thread context
436 void quiesce() { actualTC->quiesce(); }
437
438 /// Quiesce, suspend, and schedule activate at resume
439 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
440
441 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
442
443 void takeOverFrom(ThreadContext *oldContext)
444 { actualTC->takeOverFrom(oldContext); }
445
446 void regStats(const std::string &name) { actualTC->regStats(name); }
447
448 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
449
450 Tick readLastActivate() { return actualTC->readLastActivate(); }
451 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
452
453 void profileClear() { return actualTC->profileClear(); }
454 void profileSample() { return actualTC->profileSample(); }
455
456 // @todo: Do I need this?
457 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
458
459 void clearArchRegs() { actualTC->clearArchRegs(); }
460
461 //
462 // New accessors for new decoder.
463 //
464 uint64_t readIntReg(int reg_idx)
465 { return actualTC->readIntReg(reg_idx); }
466
467 FloatReg readFloatReg(int reg_idx)
468 { return actualTC->readFloatReg(reg_idx); }
469
470 FloatRegBits readFloatRegBits(int reg_idx)
471 { return actualTC->readFloatRegBits(reg_idx); }
472
473 const VecRegContainer& readVecReg(const RegId& reg) const
474 { return actualTC->readVecReg(reg); }
475
476 VecRegContainer& getWritableVecReg(const RegId& reg)
477 { return actualTC->getWritableVecReg(reg); }
478
479 /** Vector Register Lane Interfaces. */
480 /** @{ */
481 /** Reads source vector 8bit operand. */
482 ConstVecLane8
483 readVec8BitLaneReg(const RegId& reg) const
484 { return actualTC->readVec8BitLaneReg(reg); }
485
486 /** Reads source vector 16bit operand. */
487 ConstVecLane16
488 readVec16BitLaneReg(const RegId& reg) const
489 { return actualTC->readVec16BitLaneReg(reg); }
490
491 /** Reads source vector 32bit operand. */
492 ConstVecLane32
493 readVec32BitLaneReg(const RegId& reg) const
494 { return actualTC->readVec32BitLaneReg(reg); }
495
496 /** Reads source vector 64bit operand. */
497 ConstVecLane64
498 readVec64BitLaneReg(const RegId& reg) const
499 { return actualTC->readVec64BitLaneReg(reg); }
500
501 /** Write a lane of the destination vector register. */
502 virtual void setVecLane(const RegId& reg,
503 const LaneData<LaneSize::Byte>& val)
504 { return actualTC->setVecLane(reg, val); }
505 virtual void setVecLane(const RegId& reg,
506 const LaneData<LaneSize::TwoByte>& val)
507 { return actualTC->setVecLane(reg, val); }
508 virtual void setVecLane(const RegId& reg,
509 const LaneData<LaneSize::FourByte>& val)
510 { return actualTC->setVecLane(reg, val); }
511 virtual void setVecLane(const RegId& reg,
512 const LaneData<LaneSize::EightByte>& val)
513 { return actualTC->setVecLane(reg, val); }
514 /** @} */
515
516 const VecElem& readVecElem(const RegId& reg) const
517 { return actualTC->readVecElem(reg); }
518
519 CCReg readCCReg(int reg_idx)
520 { return actualTC->readCCReg(reg_idx); }
521
522 void setIntReg(int reg_idx, uint64_t val)
523 { actualTC->setIntReg(reg_idx, val); }
524
525 void setFloatReg(int reg_idx, FloatReg val)
526 { actualTC->setFloatReg(reg_idx, val); }
527
528 void setFloatRegBits(int reg_idx, FloatRegBits val)
529 { actualTC->setFloatRegBits(reg_idx, val); }
530
531 void setVecReg(const RegId& reg, const VecRegContainer& val)
532 { actualTC->setVecReg(reg, val); }
533
534 void setVecElem(const RegId& reg, const VecElem& val)
535 { actualTC->setVecElem(reg, val); }
536
537 void setCCReg(int reg_idx, CCReg val)
538 { actualTC->setCCReg(reg_idx, val); }
539
540 TheISA::PCState pcState() { return actualTC->pcState(); }
541
542 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
543
544 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
545
546 Addr instAddr() { return actualTC->instAddr(); }
547 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
548 MicroPC microPC() { return actualTC->microPC(); }
549
550 bool readPredicate() { return actualTC->readPredicate(); }
551
552 void setPredicate(bool val)
553 { actualTC->setPredicate(val); }
554
555 MiscReg readMiscRegNoEffect(int misc_reg) const
556 { return actualTC->readMiscRegNoEffect(misc_reg); }
557
558 MiscReg readMiscReg(int misc_reg)
559 { return actualTC->readMiscReg(misc_reg); }
560
561 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
562 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
563
564 void setMiscReg(int misc_reg, const MiscReg &val)
565 { return actualTC->setMiscReg(misc_reg, val); }
566
567 RegId flattenRegId(const RegId& regId) const
568 { return actualTC->flattenRegId(regId); }
569
570 unsigned readStCondFailures()
571 { return actualTC->readStCondFailures(); }
572
573 void setStCondFailures(unsigned sc_failures)
574 { actualTC->setStCondFailures(sc_failures); }
575
576 void syscall(int64_t callnum, Fault *fault)
577 { actualTC->syscall(callnum, fault); }
578
579 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
580
581 uint64_t readIntRegFlat(int idx)
582 { return actualTC->readIntRegFlat(idx); }
583
584 void setIntRegFlat(int idx, uint64_t val)
585 { actualTC->setIntRegFlat(idx, val); }
586
587 FloatReg readFloatRegFlat(int idx)
588 { return actualTC->readFloatRegFlat(idx); }
589
590 void setFloatRegFlat(int idx, FloatReg val)
591 { actualTC->setFloatRegFlat(idx, val); }
592
593 FloatRegBits readFloatRegBitsFlat(int idx)
594 { return actualTC->readFloatRegBitsFlat(idx); }
595
596 void setFloatRegBitsFlat(int idx, FloatRegBits val)
597 { actualTC->setFloatRegBitsFlat(idx, val); }
598
599 const VecRegContainer& readVecRegFlat(int id) const
600 { return actualTC->readVecRegFlat(id); }
601
602 VecRegContainer& getWritableVecRegFlat(int id)
603 { return actualTC->getWritableVecRegFlat(id); }
604
605 void setVecRegFlat(int idx, const VecRegContainer& val)
606 { actualTC->setVecRegFlat(idx, val); }
607
608 const VecElem& readVecElemFlat(const RegIndex& id,
609 const ElemIndex& elemIndex) const
610 { return actualTC->readVecElemFlat(id, elemIndex); }
611
612 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
613 const VecElem& val)
614 { actualTC->setVecElemFlat(id, elemIndex, val); }
615
616 CCReg readCCRegFlat(int idx)
617 { return actualTC->readCCRegFlat(idx); }
618
619 void setCCRegFlat(int idx, CCReg val)
620 { actualTC->setCCRegFlat(idx, val); }
621};
622
623/** @{ */
624/**
625 * Thread context serialization helpers
626 *
627 * These helper functions provide a way to the data in a
628 * ThreadContext. They are provided as separate helper function since
629 * implementing them as members of the ThreadContext interface would
630 * be confusing when the ThreadContext is exported via a proxy.
631 */
632
633void serialize(ThreadContext &tc, CheckpointOut &cp);
634void unserialize(ThreadContext &tc, CheckpointIn &cp);
635
636/** @} */
637
638
639/**
640 * Copy state between thread contexts in preparation for CPU handover.
641 *
642 * @note This method modifies the old thread contexts as well as the
643 * new thread context. The old thread context will have its quiesce
644 * event descheduled if it is scheduled and its status set to halted.
645 *
646 * @param new_tc Destination ThreadContext.
647 * @param old_tc Source ThreadContext.
648 */
649void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
650
651#endif
|