1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
| 1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
|
| 54#include "cpu/reg_class.hh"
|
54
55// @todo: Figure out a more architecture independent way to obtain the ITB and
56// DTB pointers.
57namespace TheISA
58{
59 class Decoder;
60 class TLB;
61}
62class BaseCPU;
63class CheckerCPU;
64class Checkpoint;
65class EndQuiesceEvent;
66class SETranslatingPortProxy;
67class FSTranslatingPortProxy;
68class PortProxy;
69class Process;
70class System;
71namespace TheISA {
72 namespace Kernel {
73 class Statistics;
74 }
75}
76
77/**
78 * ThreadContext is the external interface to all thread state for
79 * anything outside of the CPU. It provides all accessor methods to
80 * state that might be needed by external objects, ranging from
81 * register values to things such as kernel stats. It is an abstract
82 * base class; the CPU can create its own ThreadContext by either
83 * deriving from it, or using the templated ProxyThreadContext.
84 *
85 * The ThreadContext is slightly different than the ExecContext. The
86 * ThreadContext provides access to an individual thread's state; an
87 * ExecContext provides ISA access to the CPU (meaning it is
88 * implicitly multithreaded on SMT systems). Additionally the
89 * ThreadState is an abstract class that exactly defines the
90 * interface; the ExecContext is a more implicit interface that must
91 * be implemented so that the ISA can access whatever state it needs.
92 */
93class ThreadContext
94{
95 protected:
96 typedef TheISA::MachInst MachInst;
97 typedef TheISA::IntReg IntReg;
98 typedef TheISA::FloatReg FloatReg;
99 typedef TheISA::FloatRegBits FloatRegBits;
100 typedef TheISA::CCReg CCReg;
101 typedef TheISA::MiscReg MiscReg;
102 public:
103
104 enum Status
105 {
106 /// Running. Instructions should be executed only when
107 /// the context is in this state.
108 Active,
109
110 /// Temporarily inactive. Entered while waiting for
111 /// synchronization, etc.
112 Suspended,
113
114 /// Permanently shut down. Entered when target executes
115 /// m5exit pseudo-instruction. When all contexts enter
116 /// this state, the simulation will terminate.
117 Halted
118 };
119
120 virtual ~ThreadContext() { };
121
122 virtual BaseCPU *getCpuPtr() = 0;
123
124 virtual int cpuId() const = 0;
125
126 virtual uint32_t socketId() const = 0;
127
128 virtual int threadId() const = 0;
129
130 virtual void setThreadId(int id) = 0;
131
132 virtual int contextId() const = 0;
133
134 virtual void setContextId(int id) = 0;
135
136 virtual TheISA::TLB *getITBPtr() = 0;
137
138 virtual TheISA::TLB *getDTBPtr() = 0;
139
140 virtual CheckerCPU *getCheckerCpuPtr() = 0;
141
142 virtual TheISA::Decoder *getDecoderPtr() = 0;
143
144 virtual System *getSystemPtr() = 0;
145
146 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
147
148 virtual PortProxy &getPhysProxy() = 0;
149
150 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
151
152 /**
153 * Initialise the physical and virtual port proxies and tie them to
154 * the data port of the CPU.
155 *
156 * tc ThreadContext for the virtual-to-physical translation
157 */
158 virtual void initMemProxies(ThreadContext *tc) = 0;
159
160 virtual SETranslatingPortProxy &getMemProxy() = 0;
161
162 virtual Process *getProcessPtr() = 0;
163
164 virtual void setProcessPtr(Process *p) = 0;
165
166 virtual Status status() const = 0;
167
168 virtual void setStatus(Status new_status) = 0;
169
170 /// Set the status to Active.
171 virtual void activate() = 0;
172
173 /// Set the status to Suspended.
174 virtual void suspend() = 0;
175
176 /// Set the status to Halted.
177 virtual void halt() = 0;
178
179 /// Quiesce thread context
180 void quiesce();
181
182 /// Quiesce, suspend, and schedule activate at resume
183 void quiesceTick(Tick resume);
184
185 virtual void dumpFuncProfile() = 0;
186
187 virtual void takeOverFrom(ThreadContext *old_context) = 0;
188
189 virtual void regStats(const std::string &name) = 0;
190
191 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
192
193 // Not necessarily the best location for these...
194 // Having an extra function just to read these is obnoxious
195 virtual Tick readLastActivate() = 0;
196 virtual Tick readLastSuspend() = 0;
197
198 virtual void profileClear() = 0;
199 virtual void profileSample() = 0;
200
201 virtual void copyArchRegs(ThreadContext *tc) = 0;
202
203 virtual void clearArchRegs() = 0;
204
205 //
206 // New accessors for new decoder.
207 //
208 virtual uint64_t readIntReg(int reg_idx) = 0;
209
210 virtual FloatReg readFloatReg(int reg_idx) = 0;
211
212 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
213
214 virtual CCReg readCCReg(int reg_idx) = 0;
215
216 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
217
218 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
219
220 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
221
222 virtual void setCCReg(int reg_idx, CCReg val) = 0;
223
224 virtual TheISA::PCState pcState() = 0;
225
226 virtual void pcState(const TheISA::PCState &val) = 0;
227
228 void
229 setNPC(Addr val)
230 {
231 TheISA::PCState pc_state = pcState();
232 pc_state.setNPC(val);
233 pcState(pc_state);
234 }
235
236 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
237
238 virtual Addr instAddr() = 0;
239
240 virtual Addr nextInstAddr() = 0;
241
242 virtual MicroPC microPC() = 0;
243
244 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
245
246 virtual MiscReg readMiscReg(int misc_reg) = 0;
247
248 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
249
250 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
251
252 virtual int flattenIntIndex(int reg) = 0;
253 virtual int flattenFloatIndex(int reg) = 0;
254 virtual int flattenCCIndex(int reg) = 0;
255 virtual int flattenMiscIndex(int reg) = 0;
256
257 virtual uint64_t
| 55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60 class Decoder;
61 class TLB;
62}
63class BaseCPU;
64class CheckerCPU;
65class Checkpoint;
66class EndQuiesceEvent;
67class SETranslatingPortProxy;
68class FSTranslatingPortProxy;
69class PortProxy;
70class Process;
71class System;
72namespace TheISA {
73 namespace Kernel {
74 class Statistics;
75 }
76}
77
78/**
79 * ThreadContext is the external interface to all thread state for
80 * anything outside of the CPU. It provides all accessor methods to
81 * state that might be needed by external objects, ranging from
82 * register values to things such as kernel stats. It is an abstract
83 * base class; the CPU can create its own ThreadContext by either
84 * deriving from it, or using the templated ProxyThreadContext.
85 *
86 * The ThreadContext is slightly different than the ExecContext. The
87 * ThreadContext provides access to an individual thread's state; an
88 * ExecContext provides ISA access to the CPU (meaning it is
89 * implicitly multithreaded on SMT systems). Additionally the
90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::IntReg IntReg;
99 typedef TheISA::FloatReg FloatReg;
100 typedef TheISA::FloatRegBits FloatRegBits;
101 typedef TheISA::CCReg CCReg;
102 typedef TheISA::MiscReg MiscReg;
103 public:
104
105 enum Status
106 {
107 /// Running. Instructions should be executed only when
108 /// the context is in this state.
109 Active,
110
111 /// Temporarily inactive. Entered while waiting for
112 /// synchronization, etc.
113 Suspended,
114
115 /// Permanently shut down. Entered when target executes
116 /// m5exit pseudo-instruction. When all contexts enter
117 /// this state, the simulation will terminate.
118 Halted
119 };
120
121 virtual ~ThreadContext() { };
122
123 virtual BaseCPU *getCpuPtr() = 0;
124
125 virtual int cpuId() const = 0;
126
127 virtual uint32_t socketId() const = 0;
128
129 virtual int threadId() const = 0;
130
131 virtual void setThreadId(int id) = 0;
132
133 virtual int contextId() const = 0;
134
135 virtual void setContextId(int id) = 0;
136
137 virtual TheISA::TLB *getITBPtr() = 0;
138
139 virtual TheISA::TLB *getDTBPtr() = 0;
140
141 virtual CheckerCPU *getCheckerCpuPtr() = 0;
142
143 virtual TheISA::Decoder *getDecoderPtr() = 0;
144
145 virtual System *getSystemPtr() = 0;
146
147 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
148
149 virtual PortProxy &getPhysProxy() = 0;
150
151 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
152
153 /**
154 * Initialise the physical and virtual port proxies and tie them to
155 * the data port of the CPU.
156 *
157 * tc ThreadContext for the virtual-to-physical translation
158 */
159 virtual void initMemProxies(ThreadContext *tc) = 0;
160
161 virtual SETranslatingPortProxy &getMemProxy() = 0;
162
163 virtual Process *getProcessPtr() = 0;
164
165 virtual void setProcessPtr(Process *p) = 0;
166
167 virtual Status status() const = 0;
168
169 virtual void setStatus(Status new_status) = 0;
170
171 /// Set the status to Active.
172 virtual void activate() = 0;
173
174 /// Set the status to Suspended.
175 virtual void suspend() = 0;
176
177 /// Set the status to Halted.
178 virtual void halt() = 0;
179
180 /// Quiesce thread context
181 void quiesce();
182
183 /// Quiesce, suspend, and schedule activate at resume
184 void quiesceTick(Tick resume);
185
186 virtual void dumpFuncProfile() = 0;
187
188 virtual void takeOverFrom(ThreadContext *old_context) = 0;
189
190 virtual void regStats(const std::string &name) = 0;
191
192 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
193
194 // Not necessarily the best location for these...
195 // Having an extra function just to read these is obnoxious
196 virtual Tick readLastActivate() = 0;
197 virtual Tick readLastSuspend() = 0;
198
199 virtual void profileClear() = 0;
200 virtual void profileSample() = 0;
201
202 virtual void copyArchRegs(ThreadContext *tc) = 0;
203
204 virtual void clearArchRegs() = 0;
205
206 //
207 // New accessors for new decoder.
208 //
209 virtual uint64_t readIntReg(int reg_idx) = 0;
210
211 virtual FloatReg readFloatReg(int reg_idx) = 0;
212
213 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
214
215 virtual CCReg readCCReg(int reg_idx) = 0;
216
217 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
218
219 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
220
221 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
222
223 virtual void setCCReg(int reg_idx, CCReg val) = 0;
224
225 virtual TheISA::PCState pcState() = 0;
226
227 virtual void pcState(const TheISA::PCState &val) = 0;
228
229 void
230 setNPC(Addr val)
231 {
232 TheISA::PCState pc_state = pcState();
233 pc_state.setNPC(val);
234 pcState(pc_state);
235 }
236
237 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
238
239 virtual Addr instAddr() = 0;
240
241 virtual Addr nextInstAddr() = 0;
242
243 virtual MicroPC microPC() = 0;
244
245 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
246
247 virtual MiscReg readMiscReg(int misc_reg) = 0;
248
249 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
250
251 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
252
253 virtual int flattenIntIndex(int reg) = 0;
254 virtual int flattenFloatIndex(int reg) = 0;
255 virtual int flattenCCIndex(int reg) = 0;
256 virtual int flattenMiscIndex(int reg) = 0;
257
258 virtual uint64_t
|
258 readRegOtherThread(int misc_reg, ThreadID tid)
| 259 readRegOtherThread(RegId misc_reg, ThreadID tid)
|
259 {
260 return 0;
261 }
262
263 virtual void
| 260 {
261 return 0;
262 }
263
264 virtual void
|
264 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
| 265 setRegOtherThread(RegId misc_reg, const MiscReg &val, ThreadID tid)
|
265 {
266 }
267
268 // Also not necessarily the best location for these two. Hopefully will go
269 // away once we decide upon where st cond failures goes.
270 virtual unsigned readStCondFailures() = 0;
271
272 virtual void setStCondFailures(unsigned sc_failures) = 0;
273
274 // Same with st cond failures.
275 virtual Counter readFuncExeInst() = 0;
276
277 virtual void syscall(int64_t callnum, Fault *fault) = 0;
278
279 // This function exits the thread context in the CPU and returns
280 // 1 if the CPU has no more active threads (meaning it's OK to exit);
281 // Used in syscall-emulation mode when a thread calls the exit syscall.
282 virtual int exit() { return 1; };
283
284 /** function to compare two thread contexts (for debugging) */
285 static void compare(ThreadContext *one, ThreadContext *two);
286
287 /** @{ */
288 /**
289 * Flat register interfaces
290 *
291 * Some architectures have different registers visible in
292 * different modes. Such architectures "flatten" a register (see
293 * flattenIntIndex() and flattenFloatIndex()) to map it into the
294 * gem5 register file. This interface provides a flat interface to
295 * the underlying register file, which allows for example
296 * serialization code to access all registers.
297 */
298
299 virtual uint64_t readIntRegFlat(int idx) = 0;
300 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
301
302 virtual FloatReg readFloatRegFlat(int idx) = 0;
303 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
304
305 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
306 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
307
308 virtual CCReg readCCRegFlat(int idx) = 0;
309 virtual void setCCRegFlat(int idx, CCReg val) = 0;
310 /** @} */
311
312};
313
314/**
315 * ProxyThreadContext class that provides a way to implement a
316 * ThreadContext without having to derive from it. ThreadContext is an
317 * abstract class, so anything that derives from it and uses its
318 * interface will pay the overhead of virtual function calls. This
319 * class is created to enable a user-defined Thread object to be used
320 * wherever ThreadContexts are used, without paying the overhead of
321 * virtual function calls when it is used by itself. See
322 * simple_thread.hh for an example of this.
323 */
324template <class TC>
325class ProxyThreadContext : public ThreadContext
326{
327 public:
328 ProxyThreadContext(TC *actual_tc)
329 { actualTC = actual_tc; }
330
331 private:
332 TC *actualTC;
333
334 public:
335
336 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
337
338 int cpuId() const { return actualTC->cpuId(); }
339
340 uint32_t socketId() const { return actualTC->socketId(); }
341
342 int threadId() const { return actualTC->threadId(); }
343
344 void setThreadId(int id) { actualTC->setThreadId(id); }
345
346 int contextId() const { return actualTC->contextId(); }
347
348 void setContextId(int id) { actualTC->setContextId(id); }
349
350 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
351
352 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
353
354 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
355
356 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
357
358 System *getSystemPtr() { return actualTC->getSystemPtr(); }
359
360 TheISA::Kernel::Statistics *getKernelStats()
361 { return actualTC->getKernelStats(); }
362
363 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
364
365 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
366
367 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
368
369 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
370
371 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
372
373 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
374
375 Status status() const { return actualTC->status(); }
376
377 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
378
379 /// Set the status to Active.
380 void activate() { actualTC->activate(); }
381
382 /// Set the status to Suspended.
383 void suspend() { actualTC->suspend(); }
384
385 /// Set the status to Halted.
386 void halt() { actualTC->halt(); }
387
388 /// Quiesce thread context
389 void quiesce() { actualTC->quiesce(); }
390
391 /// Quiesce, suspend, and schedule activate at resume
392 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
393
394 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
395
396 void takeOverFrom(ThreadContext *oldContext)
397 { actualTC->takeOverFrom(oldContext); }
398
399 void regStats(const std::string &name) { actualTC->regStats(name); }
400
401 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
402
403 Tick readLastActivate() { return actualTC->readLastActivate(); }
404 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
405
406 void profileClear() { return actualTC->profileClear(); }
407 void profileSample() { return actualTC->profileSample(); }
408
409 // @todo: Do I need this?
410 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
411
412 void clearArchRegs() { actualTC->clearArchRegs(); }
413
414 //
415 // New accessors for new decoder.
416 //
417 uint64_t readIntReg(int reg_idx)
418 { return actualTC->readIntReg(reg_idx); }
419
420 FloatReg readFloatReg(int reg_idx)
421 { return actualTC->readFloatReg(reg_idx); }
422
423 FloatRegBits readFloatRegBits(int reg_idx)
424 { return actualTC->readFloatRegBits(reg_idx); }
425
426 CCReg readCCReg(int reg_idx)
427 { return actualTC->readCCReg(reg_idx); }
428
429 void setIntReg(int reg_idx, uint64_t val)
430 { actualTC->setIntReg(reg_idx, val); }
431
432 void setFloatReg(int reg_idx, FloatReg val)
433 { actualTC->setFloatReg(reg_idx, val); }
434
435 void setFloatRegBits(int reg_idx, FloatRegBits val)
436 { actualTC->setFloatRegBits(reg_idx, val); }
437
438 void setCCReg(int reg_idx, CCReg val)
439 { actualTC->setCCReg(reg_idx, val); }
440
441 TheISA::PCState pcState() { return actualTC->pcState(); }
442
443 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
444
445 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
446
447 Addr instAddr() { return actualTC->instAddr(); }
448 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
449 MicroPC microPC() { return actualTC->microPC(); }
450
451 bool readPredicate() { return actualTC->readPredicate(); }
452
453 void setPredicate(bool val)
454 { actualTC->setPredicate(val); }
455
456 MiscReg readMiscRegNoEffect(int misc_reg) const
457 { return actualTC->readMiscRegNoEffect(misc_reg); }
458
459 MiscReg readMiscReg(int misc_reg)
460 { return actualTC->readMiscReg(misc_reg); }
461
462 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
463 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
464
465 void setMiscReg(int misc_reg, const MiscReg &val)
466 { return actualTC->setMiscReg(misc_reg, val); }
467
468 int flattenIntIndex(int reg)
469 { return actualTC->flattenIntIndex(reg); }
470
471 int flattenFloatIndex(int reg)
472 { return actualTC->flattenFloatIndex(reg); }
473
474 int flattenCCIndex(int reg)
475 { return actualTC->flattenCCIndex(reg); }
476
477 int flattenMiscIndex(int reg)
478 { return actualTC->flattenMiscIndex(reg); }
479
480 unsigned readStCondFailures()
481 { return actualTC->readStCondFailures(); }
482
483 void setStCondFailures(unsigned sc_failures)
484 { actualTC->setStCondFailures(sc_failures); }
485
486 void syscall(int64_t callnum, Fault *fault)
487 { actualTC->syscall(callnum, fault); }
488
489 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
490
491 uint64_t readIntRegFlat(int idx)
492 { return actualTC->readIntRegFlat(idx); }
493
494 void setIntRegFlat(int idx, uint64_t val)
495 { actualTC->setIntRegFlat(idx, val); }
496
497 FloatReg readFloatRegFlat(int idx)
498 { return actualTC->readFloatRegFlat(idx); }
499
500 void setFloatRegFlat(int idx, FloatReg val)
501 { actualTC->setFloatRegFlat(idx, val); }
502
503 FloatRegBits readFloatRegBitsFlat(int idx)
504 { return actualTC->readFloatRegBitsFlat(idx); }
505
506 void setFloatRegBitsFlat(int idx, FloatRegBits val)
507 { actualTC->setFloatRegBitsFlat(idx, val); }
508
509 CCReg readCCRegFlat(int idx)
510 { return actualTC->readCCRegFlat(idx); }
511
512 void setCCRegFlat(int idx, CCReg val)
513 { actualTC->setCCRegFlat(idx, val); }
514};
515
516/** @{ */
517/**
518 * Thread context serialization helpers
519 *
520 * These helper functions provide a way to the data in a
521 * ThreadContext. They are provided as separate helper function since
522 * implementing them as members of the ThreadContext interface would
523 * be confusing when the ThreadContext is exported via a proxy.
524 */
525
526void serialize(ThreadContext &tc, CheckpointOut &cp);
527void unserialize(ThreadContext &tc, CheckpointIn &cp);
528
529/** @} */
530
531
532/**
533 * Copy state between thread contexts in preparation for CPU handover.
534 *
535 * @note This method modifies the old thread contexts as well as the
536 * new thread context. The old thread context will have its quiesce
537 * event descheduled if it is scheduled and its status set to halted.
538 *
539 * @param new_tc Destination ThreadContext.
540 * @param old_tc Source ThreadContext.
541 */
542void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
543
544#endif
| 266 {
267 }
268
269 // Also not necessarily the best location for these two. Hopefully will go
270 // away once we decide upon where st cond failures goes.
271 virtual unsigned readStCondFailures() = 0;
272
273 virtual void setStCondFailures(unsigned sc_failures) = 0;
274
275 // Same with st cond failures.
276 virtual Counter readFuncExeInst() = 0;
277
278 virtual void syscall(int64_t callnum, Fault *fault) = 0;
279
280 // This function exits the thread context in the CPU and returns
281 // 1 if the CPU has no more active threads (meaning it's OK to exit);
282 // Used in syscall-emulation mode when a thread calls the exit syscall.
283 virtual int exit() { return 1; };
284
285 /** function to compare two thread contexts (for debugging) */
286 static void compare(ThreadContext *one, ThreadContext *two);
287
288 /** @{ */
289 /**
290 * Flat register interfaces
291 *
292 * Some architectures have different registers visible in
293 * different modes. Such architectures "flatten" a register (see
294 * flattenIntIndex() and flattenFloatIndex()) to map it into the
295 * gem5 register file. This interface provides a flat interface to
296 * the underlying register file, which allows for example
297 * serialization code to access all registers.
298 */
299
300 virtual uint64_t readIntRegFlat(int idx) = 0;
301 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
302
303 virtual FloatReg readFloatRegFlat(int idx) = 0;
304 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
305
306 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
307 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
308
309 virtual CCReg readCCRegFlat(int idx) = 0;
310 virtual void setCCRegFlat(int idx, CCReg val) = 0;
311 /** @} */
312
313};
314
315/**
316 * ProxyThreadContext class that provides a way to implement a
317 * ThreadContext without having to derive from it. ThreadContext is an
318 * abstract class, so anything that derives from it and uses its
319 * interface will pay the overhead of virtual function calls. This
320 * class is created to enable a user-defined Thread object to be used
321 * wherever ThreadContexts are used, without paying the overhead of
322 * virtual function calls when it is used by itself. See
323 * simple_thread.hh for an example of this.
324 */
325template <class TC>
326class ProxyThreadContext : public ThreadContext
327{
328 public:
329 ProxyThreadContext(TC *actual_tc)
330 { actualTC = actual_tc; }
331
332 private:
333 TC *actualTC;
334
335 public:
336
337 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
338
339 int cpuId() const { return actualTC->cpuId(); }
340
341 uint32_t socketId() const { return actualTC->socketId(); }
342
343 int threadId() const { return actualTC->threadId(); }
344
345 void setThreadId(int id) { actualTC->setThreadId(id); }
346
347 int contextId() const { return actualTC->contextId(); }
348
349 void setContextId(int id) { actualTC->setContextId(id); }
350
351 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
352
353 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
354
355 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
356
357 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
358
359 System *getSystemPtr() { return actualTC->getSystemPtr(); }
360
361 TheISA::Kernel::Statistics *getKernelStats()
362 { return actualTC->getKernelStats(); }
363
364 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
365
366 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
367
368 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
369
370 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
371
372 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
373
374 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
375
376 Status status() const { return actualTC->status(); }
377
378 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
379
380 /// Set the status to Active.
381 void activate() { actualTC->activate(); }
382
383 /// Set the status to Suspended.
384 void suspend() { actualTC->suspend(); }
385
386 /// Set the status to Halted.
387 void halt() { actualTC->halt(); }
388
389 /// Quiesce thread context
390 void quiesce() { actualTC->quiesce(); }
391
392 /// Quiesce, suspend, and schedule activate at resume
393 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
394
395 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
396
397 void takeOverFrom(ThreadContext *oldContext)
398 { actualTC->takeOverFrom(oldContext); }
399
400 void regStats(const std::string &name) { actualTC->regStats(name); }
401
402 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
403
404 Tick readLastActivate() { return actualTC->readLastActivate(); }
405 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
406
407 void profileClear() { return actualTC->profileClear(); }
408 void profileSample() { return actualTC->profileSample(); }
409
410 // @todo: Do I need this?
411 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
412
413 void clearArchRegs() { actualTC->clearArchRegs(); }
414
415 //
416 // New accessors for new decoder.
417 //
418 uint64_t readIntReg(int reg_idx)
419 { return actualTC->readIntReg(reg_idx); }
420
421 FloatReg readFloatReg(int reg_idx)
422 { return actualTC->readFloatReg(reg_idx); }
423
424 FloatRegBits readFloatRegBits(int reg_idx)
425 { return actualTC->readFloatRegBits(reg_idx); }
426
427 CCReg readCCReg(int reg_idx)
428 { return actualTC->readCCReg(reg_idx); }
429
430 void setIntReg(int reg_idx, uint64_t val)
431 { actualTC->setIntReg(reg_idx, val); }
432
433 void setFloatReg(int reg_idx, FloatReg val)
434 { actualTC->setFloatReg(reg_idx, val); }
435
436 void setFloatRegBits(int reg_idx, FloatRegBits val)
437 { actualTC->setFloatRegBits(reg_idx, val); }
438
439 void setCCReg(int reg_idx, CCReg val)
440 { actualTC->setCCReg(reg_idx, val); }
441
442 TheISA::PCState pcState() { return actualTC->pcState(); }
443
444 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
445
446 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
447
448 Addr instAddr() { return actualTC->instAddr(); }
449 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
450 MicroPC microPC() { return actualTC->microPC(); }
451
452 bool readPredicate() { return actualTC->readPredicate(); }
453
454 void setPredicate(bool val)
455 { actualTC->setPredicate(val); }
456
457 MiscReg readMiscRegNoEffect(int misc_reg) const
458 { return actualTC->readMiscRegNoEffect(misc_reg); }
459
460 MiscReg readMiscReg(int misc_reg)
461 { return actualTC->readMiscReg(misc_reg); }
462
463 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
464 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
465
466 void setMiscReg(int misc_reg, const MiscReg &val)
467 { return actualTC->setMiscReg(misc_reg, val); }
468
469 int flattenIntIndex(int reg)
470 { return actualTC->flattenIntIndex(reg); }
471
472 int flattenFloatIndex(int reg)
473 { return actualTC->flattenFloatIndex(reg); }
474
475 int flattenCCIndex(int reg)
476 { return actualTC->flattenCCIndex(reg); }
477
478 int flattenMiscIndex(int reg)
479 { return actualTC->flattenMiscIndex(reg); }
480
481 unsigned readStCondFailures()
482 { return actualTC->readStCondFailures(); }
483
484 void setStCondFailures(unsigned sc_failures)
485 { actualTC->setStCondFailures(sc_failures); }
486
487 void syscall(int64_t callnum, Fault *fault)
488 { actualTC->syscall(callnum, fault); }
489
490 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
491
492 uint64_t readIntRegFlat(int idx)
493 { return actualTC->readIntRegFlat(idx); }
494
495 void setIntRegFlat(int idx, uint64_t val)
496 { actualTC->setIntRegFlat(idx, val); }
497
498 FloatReg readFloatRegFlat(int idx)
499 { return actualTC->readFloatRegFlat(idx); }
500
501 void setFloatRegFlat(int idx, FloatReg val)
502 { actualTC->setFloatRegFlat(idx, val); }
503
504 FloatRegBits readFloatRegBitsFlat(int idx)
505 { return actualTC->readFloatRegBitsFlat(idx); }
506
507 void setFloatRegBitsFlat(int idx, FloatRegBits val)
508 { actualTC->setFloatRegBitsFlat(idx, val); }
509
510 CCReg readCCRegFlat(int idx)
511 { return actualTC->readCCRegFlat(idx); }
512
513 void setCCRegFlat(int idx, CCReg val)
514 { actualTC->setCCRegFlat(idx, val); }
515};
516
517/** @{ */
518/**
519 * Thread context serialization helpers
520 *
521 * These helper functions provide a way to the data in a
522 * ThreadContext. They are provided as separate helper function since
523 * implementing them as members of the ThreadContext interface would
524 * be confusing when the ThreadContext is exported via a proxy.
525 */
526
527void serialize(ThreadContext &tc, CheckpointOut &cp);
528void unserialize(ThreadContext &tc, CheckpointIn &cp);
529
530/** @} */
531
532
533/**
534 * Copy state between thread contexts in preparation for CPU handover.
535 *
536 * @note This method modifies the old thread contexts as well as the
537 * new thread context. The old thread context will have its quiesce
538 * event descheduled if it is scheduled and its status set to halted.
539 *
540 * @param new_tc Destination ThreadContext.
541 * @param old_tc Source ThreadContext.
542 */
543void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
544
545#endif
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