1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include "arch/regfile.hh"
35#include "arch/types.hh"
36#include "base/types.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
39#include "sim/byteswap.hh"
40#include "sim/faults.hh"
41#include "sim/serialize.hh"
42
43// @todo: Figure out a more architecture independent way to obtain the ITB and
44// DTB pointers.
45namespace TheISA
46{
47 class TLB;
48}
49class BaseCPU;
50class EndQuiesceEvent;
51class Event;
52class TranslatingPort;
53class FunctionalPort;
54class VirtualPort;
55class Process;
56class System;
57namespace TheISA {
58 namespace Kernel {
59 class Statistics;
60 };
61};
62
63/**
64 * ThreadContext is the external interface to all thread state for
65 * anything outside of the CPU. It provides all accessor methods to
66 * state that might be needed by external objects, ranging from
67 * register values to things such as kernel stats. It is an abstract
68 * base class; the CPU can create its own ThreadContext by either
69 * deriving from it, or using the templated ProxyThreadContext.
70 *
71 * The ThreadContext is slightly different than the ExecContext. The
72 * ThreadContext provides access to an individual thread's state; an
73 * ExecContext provides ISA access to the CPU (meaning it is
74 * implicitly multithreaded on SMT systems). Additionally the
75 * ThreadState is an abstract class that exactly defines the
76 * interface; the ExecContext is a more implicit interface that must
77 * be implemented so that the ISA can access whatever state it needs.
78 */
79class ThreadContext
80{
81 protected:
82 typedef TheISA::RegFile RegFile;
83 typedef TheISA::MachInst MachInst;
84 typedef TheISA::IntReg IntReg;
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
87 typedef TheISA::MiscRegFile MiscRegFile;
88 typedef TheISA::MiscReg MiscReg;
89 public:
90
91 enum Status
92 {
93 /// Running. Instructions should be executed only when
94 /// the context is in this state.
95 Active,
96
97 /// Temporarily inactive. Entered while waiting for
98 /// synchronization, etc.
99 Suspended,
100
101 /// Permanently shut down. Entered when target executes
102 /// m5exit pseudo-instruction. When all contexts enter
103 /// this state, the simulation will terminate.
104 Halted
105 };
106
107 virtual ~ThreadContext() { };
108
109 virtual BaseCPU *getCpuPtr() = 0;
110
111 virtual int cpuId() = 0;
112
113 virtual int threadId() = 0;
114
115 virtual void setThreadId(int id) = 0;
116
117 virtual int contextId() = 0;
118
119 virtual void setContextId(int id) = 0;
120
121 virtual TheISA::TLB *getITBPtr() = 0;
122
123 virtual TheISA::TLB *getDTBPtr() = 0;
124
125 virtual System *getSystemPtr() = 0;
126
127#if FULL_SYSTEM
128 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
129
130 virtual FunctionalPort *getPhysPort() = 0;
131
132 virtual VirtualPort *getVirtPort() = 0;
133
134 virtual void connectMemPorts(ThreadContext *tc) = 0;
135#else
136 virtual TranslatingPort *getMemPort() = 0;
137
138 virtual Process *getProcessPtr() = 0;
139#endif
140
141 virtual Status status() const = 0;
142
143 virtual void setStatus(Status new_status) = 0;
144
145 /// Set the status to Active. Optional delay indicates number of
146 /// cycles to wait before beginning execution.
147 virtual void activate(int delay = 1) = 0;
148
149 /// Set the status to Suspended.
150 virtual void suspend(int delay = 0) = 0;
151
152 /// Set the status to Halted.
153 virtual void halt(int delay = 0) = 0;
154
155#if FULL_SYSTEM
156 virtual void dumpFuncProfile() = 0;
157#endif
158
159 virtual void takeOverFrom(ThreadContext *old_context) = 0;
160
161 virtual void regStats(const std::string &name) = 0;
162
163 virtual void serialize(std::ostream &os) = 0;
164 virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
165
166#if FULL_SYSTEM
167 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
168
169 // Not necessarily the best location for these...
170 // Having an extra function just to read these is obnoxious
171 virtual Tick readLastActivate() = 0;
172 virtual Tick readLastSuspend() = 0;
173
174 virtual void profileClear() = 0;
175 virtual void profileSample() = 0;
176#endif
177
178 // Also somewhat obnoxious. Really only used for the TLB fault.
179 // However, may be quite useful in SPARC.
180 virtual TheISA::MachInst getInst() = 0;
181
182 virtual void copyArchRegs(ThreadContext *tc) = 0;
183
184 virtual void clearArchRegs() = 0;
185
186 //
187 // New accessors for new decoder.
188 //
189 virtual uint64_t readIntReg(int reg_idx) = 0;
190
191 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
192
193 virtual FloatReg readFloatReg(int reg_idx) = 0;
194
195 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
196
197 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
198
199 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
200
201 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
202
203 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
204
205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
206
207 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
208
209 virtual uint64_t readPC() = 0;
210
211 virtual void setPC(uint64_t val) = 0;
212
213 virtual uint64_t readNextPC() = 0;
214
215 virtual void setNextPC(uint64_t val) = 0;
216
217 virtual uint64_t readNextNPC() = 0;
218
219 virtual void setNextNPC(uint64_t val) = 0;
220
221 virtual uint64_t readMicroPC() = 0;
222
223 virtual void setMicroPC(uint64_t val) = 0;
224
225 virtual uint64_t readNextMicroPC() = 0;
226
227 virtual void setNextMicroPC(uint64_t val) = 0;
228
229 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
230
231 virtual MiscReg readMiscReg(int misc_reg) = 0;
232
233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
234
235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
236
237 virtual uint64_t
238 readRegOtherThread(int misc_reg, ThreadID tid)
239 {
240 return 0;
241 }
242
243 virtual void
244 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
245 {
246 }
247
248 // Also not necessarily the best location for these two. Hopefully will go
249 // away once we decide upon where st cond failures goes.
250 virtual unsigned readStCondFailures() = 0;
251
252 virtual void setStCondFailures(unsigned sc_failures) = 0;
253
254 // Only really makes sense for old CPU model. Still could be useful though.
255 virtual bool misspeculating() = 0;
256
257#if !FULL_SYSTEM
258 // Same with st cond failures.
259 virtual Counter readFuncExeInst() = 0;
260
261 virtual void syscall(int64_t callnum) = 0;
262
263 // This function exits the thread context in the CPU and returns
264 // 1 if the CPU has no more active threads (meaning it's OK to exit);
265 // Used in syscall-emulation mode when a thread calls the exit syscall.
266 virtual int exit() { return 1; };
267#endif
268
269 /** function to compare two thread contexts (for debugging) */
270 static void compare(ThreadContext *one, ThreadContext *two);
271};
272
273/**
274 * ProxyThreadContext class that provides a way to implement a
275 * ThreadContext without having to derive from it. ThreadContext is an
276 * abstract class, so anything that derives from it and uses its
277 * interface will pay the overhead of virtual function calls. This
278 * class is created to enable a user-defined Thread object to be used
279 * wherever ThreadContexts are used, without paying the overhead of
280 * virtual function calls when it is used by itself. See
281 * simple_thread.hh for an example of this.
282 */
283template <class TC>
284class ProxyThreadContext : public ThreadContext
285{
286 public:
287 ProxyThreadContext(TC *actual_tc)
288 { actualTC = actual_tc; }
289
290 private:
291 TC *actualTC;
292
293 public:
294
295 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
296
297 int cpuId() { return actualTC->cpuId(); }
298
299 int threadId() { return actualTC->threadId(); }
300
301 void setThreadId(int id) { return actualTC->setThreadId(id); }
302
303 int contextId() { return actualTC->contextId(); }
304
305 void setContextId(int id) { actualTC->setContextId(id); }
306
307 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
308
309 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
310
311 System *getSystemPtr() { return actualTC->getSystemPtr(); }
312
313#if FULL_SYSTEM
314 TheISA::Kernel::Statistics *getKernelStats()
315 { return actualTC->getKernelStats(); }
316
317 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
318
319 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
320
321 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
322#else
323 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
324
325 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
326#endif
327
328 Status status() const { return actualTC->status(); }
329
330 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
331
332 /// Set the status to Active. Optional delay indicates number of
333 /// cycles to wait before beginning execution.
334 void activate(int delay = 1) { actualTC->activate(delay); }
335
336 /// Set the status to Suspended.
337 void suspend(int delay = 0) { actualTC->suspend(); }
338
339 /// Set the status to Halted.
340 void halt(int delay = 0) { actualTC->halt(); }
341
342#if FULL_SYSTEM
343 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
344#endif
345
346 void takeOverFrom(ThreadContext *oldContext)
347 { actualTC->takeOverFrom(oldContext); }
348
349 void regStats(const std::string &name) { actualTC->regStats(name); }
350
351 void serialize(std::ostream &os) { actualTC->serialize(os); }
352 void unserialize(Checkpoint *cp, const std::string &section)
353 { actualTC->unserialize(cp, section); }
354
355#if FULL_SYSTEM
356 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
357
358 Tick readLastActivate() { return actualTC->readLastActivate(); }
359 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
360
361 void profileClear() { return actualTC->profileClear(); }
362 void profileSample() { return actualTC->profileSample(); }
363#endif
364 // @todo: Do I need this?
365 MachInst getInst() { return actualTC->getInst(); }
366
367 // @todo: Do I need this?
368 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
369
370 void clearArchRegs() { actualTC->clearArchRegs(); }
371
372 //
373 // New accessors for new decoder.
374 //
375 uint64_t readIntReg(int reg_idx)
376 { return actualTC->readIntReg(reg_idx); }
377
378 FloatReg readFloatReg(int reg_idx, int width)
379 { return actualTC->readFloatReg(reg_idx, width); }
380
381 FloatReg readFloatReg(int reg_idx)
382 { return actualTC->readFloatReg(reg_idx); }
383
384 FloatRegBits readFloatRegBits(int reg_idx, int width)
385 { return actualTC->readFloatRegBits(reg_idx, width); }
386
387 FloatRegBits readFloatRegBits(int reg_idx)
388 { return actualTC->readFloatRegBits(reg_idx); }
389
390 void setIntReg(int reg_idx, uint64_t val)
391 { actualTC->setIntReg(reg_idx, val); }
392
393 void setFloatReg(int reg_idx, FloatReg val, int width)
394 { actualTC->setFloatReg(reg_idx, val, width); }
395
396 void setFloatReg(int reg_idx, FloatReg val)
397 { actualTC->setFloatReg(reg_idx, val); }
398
399 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
400 { actualTC->setFloatRegBits(reg_idx, val, width); }
401
402 void setFloatRegBits(int reg_idx, FloatRegBits val)
403 { actualTC->setFloatRegBits(reg_idx, val); }
404
405 uint64_t readPC() { return actualTC->readPC(); }
406
407 void setPC(uint64_t val) { actualTC->setPC(val); }
408
409 uint64_t readNextPC() { return actualTC->readNextPC(); }
410
411 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
412
413 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
414
415 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
416
417 uint64_t readMicroPC() { return actualTC->readMicroPC(); }
418
419 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
420
421 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
422
423 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
424
425 MiscReg readMiscRegNoEffect(int misc_reg)
426 { return actualTC->readMiscRegNoEffect(misc_reg); }
427
428 MiscReg readMiscReg(int misc_reg)
429 { return actualTC->readMiscReg(misc_reg); }
430
431 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
432 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
433
434 void setMiscReg(int misc_reg, const MiscReg &val)
435 { return actualTC->setMiscReg(misc_reg, val); }
436
437 unsigned readStCondFailures()
438 { return actualTC->readStCondFailures(); }
439
440 void setStCondFailures(unsigned sc_failures)
441 { actualTC->setStCondFailures(sc_failures); }
442
443 // @todo: Fix this!
444 bool misspeculating() { return actualTC->misspeculating(); }
445
446#if !FULL_SYSTEM
447 void syscall(int64_t callnum)
448 { actualTC->syscall(callnum); }
449
450 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
451#endif
452};
453
454#endif