1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/reg_class.hh"
55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60 class Decoder;
61}
62class BaseCPU;
63class BaseTLB;
64class CheckerCPU;
65class Checkpoint;
66class EndQuiesceEvent;
67class SETranslatingPortProxy;
68class FSTranslatingPortProxy;
69class PortProxy;
70class Process;
71class System;
72namespace TheISA {
73 namespace Kernel {
74 class Statistics;
75 }
76}
77
78/**
79 * ThreadContext is the external interface to all thread state for
80 * anything outside of the CPU. It provides all accessor methods to
81 * state that might be needed by external objects, ranging from
82 * register values to things such as kernel stats. It is an abstract
83 * base class; the CPU can create its own ThreadContext by either
84 * deriving from it, or using the templated ProxyThreadContext.
85 *
86 * The ThreadContext is slightly different than the ExecContext. The
87 * ThreadContext provides access to an individual thread's state; an
88 * ExecContext provides ISA access to the CPU (meaning it is
89 * implicitly multithreaded on SMT systems). Additionally the
90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 using VecRegContainer = TheISA::VecRegContainer;
99 using VecElem = TheISA::VecElem;
100 using VecPredRegContainer = TheISA::VecPredRegContainer;
101
102 public:
103
104 enum Status
105 {
106 /// Running. Instructions should be executed only when
107 /// the context is in this state.
108 Active,
109
110 /// Temporarily inactive. Entered while waiting for
111 /// synchronization, etc.
112 Suspended,
113
114 /// Trying to exit and waiting for an event to completely exit.
115 /// Entered when target executes an exit syscall.
116 Halting,
117
118 /// Permanently shut down. Entered when target executes
119 /// m5exit pseudo-instruction. When all contexts enter
120 /// this state, the simulation will terminate.
121 Halted
122 };
123
124 virtual ~ThreadContext() { };
125
126 virtual BaseCPU *getCpuPtr() = 0;
127
128 virtual int cpuId() const = 0;
129
130 virtual uint32_t socketId() const = 0;
131
132 virtual int threadId() const = 0;
133
134 virtual void setThreadId(int id) = 0;
135
136 virtual int contextId() const = 0;
137
138 virtual void setContextId(int id) = 0;
139
140 virtual BaseTLB *getITBPtr() = 0;
141
142 virtual BaseTLB *getDTBPtr() = 0;
143
144 virtual CheckerCPU *getCheckerCpuPtr() = 0;
145
146 virtual TheISA::Decoder *getDecoderPtr() = 0;
147
148 virtual System *getSystemPtr() = 0;
149
150 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
151
152 virtual PortProxy &getPhysProxy() = 0;
153
154 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
155
156 /**
157 * Initialise the physical and virtual port proxies and tie them to
158 * the data port of the CPU.
159 *
160 * tc ThreadContext for the virtual-to-physical translation
161 */
162 virtual void initMemProxies(ThreadContext *tc) = 0;
163
164 virtual SETranslatingPortProxy &getMemProxy() = 0;
165
166 virtual Process *getProcessPtr() = 0;
167
168 virtual void setProcessPtr(Process *p) = 0;
169
170 virtual Status status() const = 0;
171
172 virtual void setStatus(Status new_status) = 0;
173
174 /// Set the status to Active.
175 virtual void activate() = 0;
176
177 /// Set the status to Suspended.
178 virtual void suspend() = 0;
179
180 /// Set the status to Halted.
181 virtual void halt() = 0;
182
183 /// Quiesce thread context
184 void quiesce();
185
186 /// Quiesce, suspend, and schedule activate at resume
187 void quiesceTick(Tick resume);
188
189 virtual void dumpFuncProfile() = 0;
190
191 virtual void takeOverFrom(ThreadContext *old_context) = 0;
192
193 virtual void regStats(const std::string &name) = 0;
194
195 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
196
197 // Not necessarily the best location for these...
198 // Having an extra function just to read these is obnoxious
199 virtual Tick readLastActivate() = 0;
200 virtual Tick readLastSuspend() = 0;
201
202 virtual void profileClear() = 0;
203 virtual void profileSample() = 0;
204
205 virtual void copyArchRegs(ThreadContext *tc) = 0;
206
207 virtual void clearArchRegs() = 0;
208
209 //
210 // New accessors for new decoder.
211 //
212 virtual RegVal readIntReg(int reg_idx) = 0;
213
214 virtual RegVal readFloatReg(int reg_idx) = 0;
215
216 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
217 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
218
219 /** Vector Register Lane Interfaces. */
220 /** @{ */
221 /** Reads source vector 8bit operand. */
222 virtual ConstVecLane8
223 readVec8BitLaneReg(const RegId& reg) const = 0;
224
225 /** Reads source vector 16bit operand. */
226 virtual ConstVecLane16
227 readVec16BitLaneReg(const RegId& reg) const = 0;
228
229 /** Reads source vector 32bit operand. */
230 virtual ConstVecLane32
231 readVec32BitLaneReg(const RegId& reg) const = 0;
232
233 /** Reads source vector 64bit operand. */
234 virtual ConstVecLane64
235 readVec64BitLaneReg(const RegId& reg) const = 0;
236
237 /** Write a lane of the destination vector register. */
238 virtual void setVecLane(const RegId& reg,
239 const LaneData<LaneSize::Byte>& val) = 0;
240 virtual void setVecLane(const RegId& reg,
241 const LaneData<LaneSize::TwoByte>& val) = 0;
242 virtual void setVecLane(const RegId& reg,
243 const LaneData<LaneSize::FourByte>& val) = 0;
244 virtual void setVecLane(const RegId& reg,
245 const LaneData<LaneSize::EightByte>& val) = 0;
246 /** @} */
247
248 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
249
250 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
251 const = 0;
252 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
253
254 virtual RegVal readCCReg(int reg_idx) = 0;
255
256 virtual void setIntReg(int reg_idx, RegVal val) = 0;
257
258 virtual void setFloatReg(int reg_idx, RegVal val) = 0;
259
260 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
261
262 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
263
264 virtual void setVecPredReg(const RegId& reg,
265 const VecPredRegContainer& val) = 0;
266
267 virtual void setCCReg(int reg_idx, RegVal val) = 0;
268
269 virtual TheISA::PCState pcState() = 0;
270
271 virtual void pcState(const TheISA::PCState &val) = 0;
272
273 void
274 setNPC(Addr val)
275 {
276 TheISA::PCState pc_state = pcState();
277 pc_state.setNPC(val);
278 pcState(pc_state);
279 }
280
281 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
282
283 virtual Addr instAddr() = 0;
284
285 virtual Addr nextInstAddr() = 0;
286
287 virtual MicroPC microPC() = 0;
288
289 virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0;
290
291 virtual RegVal readMiscReg(int misc_reg) = 0;
292
293 virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
294
295 virtual void setMiscReg(int misc_reg, RegVal val) = 0;
296
297 virtual RegId flattenRegId(const RegId& regId) const = 0;
298
299 virtual RegVal
300 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
301 {
302 return 0;
303 }
304
305 virtual void
306 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
307 {
308 }
309
310 // Also not necessarily the best location for these two. Hopefully will go
311 // away once we decide upon where st cond failures goes.
312 virtual unsigned readStCondFailures() = 0;
313
314 virtual void setStCondFailures(unsigned sc_failures) = 0;
315
316 // Same with st cond failures.
317 virtual Counter readFuncExeInst() = 0;
318
319 virtual void syscall(int64_t callnum, Fault *fault) = 0;
320
321 // This function exits the thread context in the CPU and returns
322 // 1 if the CPU has no more active threads (meaning it's OK to exit);
323 // Used in syscall-emulation mode when a thread calls the exit syscall.
324 virtual int exit() { return 1; };
325
326 /** function to compare two thread contexts (for debugging) */
327 static void compare(ThreadContext *one, ThreadContext *two);
328
329 /** @{ */
330 /**
331 * Flat register interfaces
332 *
333 * Some architectures have different registers visible in
334 * different modes. Such architectures "flatten" a register (see
335 * flattenRegId()) to map it into the
336 * gem5 register file. This interface provides a flat interface to
337 * the underlying register file, which allows for example
338 * serialization code to access all registers.
339 */
340
341 virtual RegVal readIntRegFlat(int idx) = 0;
342 virtual void setIntRegFlat(int idx, RegVal val) = 0;
343
344 virtual RegVal readFloatRegFlat(int idx) = 0;
345 virtual void setFloatRegFlat(int idx, RegVal val) = 0;
346
347 virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
348 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
349 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
350
351 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
352 const ElemIndex& elemIdx) const = 0;
353 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
354 const VecElem& val) = 0;
355
356 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0;
357 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0;
358 virtual void setVecPredRegFlat(int idx,
359 const VecPredRegContainer& val) = 0;
360
361 virtual RegVal readCCRegFlat(int idx) = 0;
362 virtual void setCCRegFlat(int idx, RegVal val) = 0;
363 /** @} */
364
365};
366
367/**
368 * ProxyThreadContext class that provides a way to implement a
369 * ThreadContext without having to derive from it. ThreadContext is an
370 * abstract class, so anything that derives from it and uses its
371 * interface will pay the overhead of virtual function calls. This
372 * class is created to enable a user-defined Thread object to be used
373 * wherever ThreadContexts are used, without paying the overhead of
374 * virtual function calls when it is used by itself. See
375 * simple_thread.hh for an example of this.
376 */
377template <class TC>
378class ProxyThreadContext : public ThreadContext
379{
380 public:
381 ProxyThreadContext(TC *actual_tc)
382 { actualTC = actual_tc; }
383
384 private:
385 TC *actualTC;
386
387 public:
388
389 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
390
391 int cpuId() const { return actualTC->cpuId(); }
392
393 uint32_t socketId() const { return actualTC->socketId(); }
394
395 int threadId() const { return actualTC->threadId(); }
396
397 void setThreadId(int id) { actualTC->setThreadId(id); }
398
399 int contextId() const { return actualTC->contextId(); }
400
401 void setContextId(int id) { actualTC->setContextId(id); }
402
403 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
404
405 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
406
407 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
408
409 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
410
411 System *getSystemPtr() { return actualTC->getSystemPtr(); }
412
413 TheISA::Kernel::Statistics *getKernelStats()
414 { return actualTC->getKernelStats(); }
415
416 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
417
418 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
419
420 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
421
422 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
423
424 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
425
426 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
427
428 Status status() const { return actualTC->status(); }
429
430 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
431
432 /// Set the status to Active.
433 void activate() { actualTC->activate(); }
434
435 /// Set the status to Suspended.
436 void suspend() { actualTC->suspend(); }
437
438 /// Set the status to Halted.
439 void halt() { actualTC->halt(); }
440
441 /// Quiesce thread context
442 void quiesce() { actualTC->quiesce(); }
443
444 /// Quiesce, suspend, and schedule activate at resume
445 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
446
447 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
448
449 void takeOverFrom(ThreadContext *oldContext)
450 { actualTC->takeOverFrom(oldContext); }
451
452 void regStats(const std::string &name) { actualTC->regStats(name); }
453
454 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
455
456 Tick readLastActivate() { return actualTC->readLastActivate(); }
457 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
458
459 void profileClear() { return actualTC->profileClear(); }
460 void profileSample() { return actualTC->profileSample(); }
461
462 // @todo: Do I need this?
463 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
464
465 void clearArchRegs() { actualTC->clearArchRegs(); }
466
467 //
468 // New accessors for new decoder.
469 //
470 RegVal readIntReg(int reg_idx)
471 { return actualTC->readIntReg(reg_idx); }
472
473 RegVal readFloatReg(int reg_idx)
474 { return actualTC->readFloatReg(reg_idx); }
475
476 const VecRegContainer& readVecReg(const RegId& reg) const
477 { return actualTC->readVecReg(reg); }
478
479 VecRegContainer& getWritableVecReg(const RegId& reg)
480 { return actualTC->getWritableVecReg(reg); }
481
482 /** Vector Register Lane Interfaces. */
483 /** @{ */
484 /** Reads source vector 8bit operand. */
485 ConstVecLane8
486 readVec8BitLaneReg(const RegId& reg) const
487 { return actualTC->readVec8BitLaneReg(reg); }
488
489 /** Reads source vector 16bit operand. */
490 ConstVecLane16
491 readVec16BitLaneReg(const RegId& reg) const
492 { return actualTC->readVec16BitLaneReg(reg); }
493
494 /** Reads source vector 32bit operand. */
495 ConstVecLane32
496 readVec32BitLaneReg(const RegId& reg) const
497 { return actualTC->readVec32BitLaneReg(reg); }
498
499 /** Reads source vector 64bit operand. */
500 ConstVecLane64
501 readVec64BitLaneReg(const RegId& reg) const
502 { return actualTC->readVec64BitLaneReg(reg); }
503
504 /** Write a lane of the destination vector register. */
505 virtual void setVecLane(const RegId& reg,
506 const LaneData<LaneSize::Byte>& val)
507 { return actualTC->setVecLane(reg, val); }
508 virtual void setVecLane(const RegId& reg,
509 const LaneData<LaneSize::TwoByte>& val)
510 { return actualTC->setVecLane(reg, val); }
511 virtual void setVecLane(const RegId& reg,
512 const LaneData<LaneSize::FourByte>& val)
513 { return actualTC->setVecLane(reg, val); }
514 virtual void setVecLane(const RegId& reg,
515 const LaneData<LaneSize::EightByte>& val)
516 { return actualTC->setVecLane(reg, val); }
517 /** @} */
518
519 const VecElem& readVecElem(const RegId& reg) const
520 { return actualTC->readVecElem(reg); }
521
522 const VecPredRegContainer& readVecPredReg(const RegId& reg) const
523 { return actualTC->readVecPredReg(reg); }
524
525 VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
526 { return actualTC->getWritableVecPredReg(reg); }
527
528 RegVal readCCReg(int reg_idx)
529 { return actualTC->readCCReg(reg_idx); }
530
531 void setIntReg(int reg_idx, RegVal val)
532 { actualTC->setIntReg(reg_idx, val); }
533
534 void setFloatReg(int reg_idx, RegVal val)
535 { actualTC->setFloatReg(reg_idx, val); }
536
537 void setVecReg(const RegId& reg, const VecRegContainer& val)
538 { actualTC->setVecReg(reg, val); }
539
540 void setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
541 { actualTC->setVecPredReg(reg, val); }
542
543 void setVecElem(const RegId& reg, const VecElem& val)
544 { actualTC->setVecElem(reg, val); }
545
546 void setCCReg(int reg_idx, RegVal val)
547 { actualTC->setCCReg(reg_idx, val); }
548
549 TheISA::PCState pcState() { return actualTC->pcState(); }
550
551 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
552
553 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
554
555 Addr instAddr() { return actualTC->instAddr(); }
556 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
557 MicroPC microPC() { return actualTC->microPC(); }
558
559 bool readPredicate() { return actualTC->readPredicate(); }
560
561 void setPredicate(bool val)
562 { actualTC->setPredicate(val); }
563
564 RegVal readMiscRegNoEffect(int misc_reg) const
565 { return actualTC->readMiscRegNoEffect(misc_reg); }
566
567 RegVal readMiscReg(int misc_reg)
568 { return actualTC->readMiscReg(misc_reg); }
569
570 void setMiscRegNoEffect(int misc_reg, RegVal val)
571 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
572
573 void setMiscReg(int misc_reg, RegVal val)
574 { return actualTC->setMiscReg(misc_reg, val); }
575
576 RegId flattenRegId(const RegId& regId) const
577 { return actualTC->flattenRegId(regId); }
578
579 unsigned readStCondFailures()
580 { return actualTC->readStCondFailures(); }
581
582 void setStCondFailures(unsigned sc_failures)
583 { actualTC->setStCondFailures(sc_failures); }
584
585 void syscall(int64_t callnum, Fault *fault)
586 { actualTC->syscall(callnum, fault); }
587
588 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
589
590 RegVal readIntRegFlat(int idx)
591 { return actualTC->readIntRegFlat(idx); }
592
593 void setIntRegFlat(int idx, RegVal val)
594 { actualTC->setIntRegFlat(idx, val); }
595
596 RegVal readFloatRegFlat(int idx)
597 { return actualTC->readFloatRegFlat(idx); }
598
599 void setFloatRegFlat(int idx, RegVal val)
600 { actualTC->setFloatRegFlat(idx, val); }
601
602 const VecRegContainer& readVecRegFlat(int id) const
603 { return actualTC->readVecRegFlat(id); }
604
605 VecRegContainer& getWritableVecRegFlat(int id)
606 { return actualTC->getWritableVecRegFlat(id); }
607
608 void setVecRegFlat(int idx, const VecRegContainer& val)
609 { actualTC->setVecRegFlat(idx, val); }
610
611 const VecElem& readVecElemFlat(const RegIndex& id,
612 const ElemIndex& elemIndex) const
613 { return actualTC->readVecElemFlat(id, elemIndex); }
614
615 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
616 const VecElem& val)
617 { actualTC->setVecElemFlat(id, elemIndex, val); }
618
619 const VecPredRegContainer& readVecPredRegFlat(int id) const
620 { return actualTC->readVecPredRegFlat(id); }
621
622 VecPredRegContainer& getWritableVecPredRegFlat(int id)
623 { return actualTC->getWritableVecPredRegFlat(id); }
624
625 void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
626 { actualTC->setVecPredRegFlat(idx, val); }
627
628 RegVal readCCRegFlat(int idx)
629 { return actualTC->readCCRegFlat(idx); }
630
631 void setCCRegFlat(int idx, RegVal val)
632 { actualTC->setCCRegFlat(idx, val); }
633};
634
635/** @{ */
636/**
637 * Thread context serialization helpers
638 *
639 * These helper functions provide a way to the data in a
640 * ThreadContext. They are provided as separate helper function since
641 * implementing them as members of the ThreadContext interface would
642 * be confusing when the ThreadContext is exported via a proxy.
643 */
644
645void serialize(ThreadContext &tc, CheckpointOut &cp);
646void unserialize(ThreadContext &tc, CheckpointIn &cp);
647
648/** @} */
649
650
651/**
652 * Copy state between thread contexts in preparation for CPU handover.
653 *
654 * @note This method modifies the old thread contexts as well as the
655 * new thread context. The old thread context will have its quiesce
656 * event descheduled if it is scheduled and its status set to halted.
657 *
658 * @param new_tc Destination ThreadContext.
659 * @param old_tc Source ThreadContext.
660 */
661void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
662
663#endif