1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

--- 82 unchanged lines hidden (view full) ---

93 */
94class ThreadContext
95{
96 protected:
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::CCReg CCReg;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
101 public:
102
103 enum Status
104 {
105 /// Running. Instructions should be executed only when
106 /// the context is in this state.
107 Active,
108

--- 128 unchanged lines hidden (view full) ---

237 virtual void setVecLane(const RegId& reg,
238 const LaneData<LaneSize::FourByte>& val) = 0;
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::EightByte>& val) = 0;
241 /** @} */
242
243 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
244
245 virtual CCReg readCCReg(int reg_idx) = 0;
246
247 virtual void setIntReg(int reg_idx, RegVal val) = 0;
248
249 virtual void setFloatRegBits(int reg_idx, RegVal val) = 0;
250
251 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
252
253 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
254
255 virtual void setCCReg(int reg_idx, CCReg val) = 0;
256
257 virtual TheISA::PCState pcState() = 0;
258
259 virtual void pcState(const TheISA::PCState &val) = 0;
260
261 void
262 setNPC(Addr val)

--- 73 unchanged lines hidden (view full) ---

336 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
337 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
338
339 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
340 const ElemIndex& elemIdx) const = 0;
341 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
342 const VecElem& val) = 0;
343
344 virtual CCReg readCCRegFlat(int idx) = 0;
345 virtual void setCCRegFlat(int idx, CCReg val) = 0;
346 /** @} */
347
348};
349
350/**
351 * ProxyThreadContext class that provides a way to implement a

--- 145 unchanged lines hidden (view full) ---

497 virtual void setVecLane(const RegId& reg,
498 const LaneData<LaneSize::EightByte>& val)
499 { return actualTC->setVecLane(reg, val); }
500 /** @} */
501
502 const VecElem& readVecElem(const RegId& reg) const
503 { return actualTC->readVecElem(reg); }
504
505 CCReg readCCReg(int reg_idx)
506 { return actualTC->readCCReg(reg_idx); }
507
508 void setIntReg(int reg_idx, RegVal val)
509 { actualTC->setIntReg(reg_idx, val); }
510
511 void setFloatRegBits(int reg_idx, RegVal val)
512 { actualTC->setFloatRegBits(reg_idx, val); }
513
514 void setVecReg(const RegId& reg, const VecRegContainer& val)
515 { actualTC->setVecReg(reg, val); }
516
517 void setVecElem(const RegId& reg, const VecElem& val)
518 { actualTC->setVecElem(reg, val); }
519
520 void setCCReg(int reg_idx, CCReg val)
521 { actualTC->setCCReg(reg_idx, val); }
522
523 TheISA::PCState pcState() { return actualTC->pcState(); }
524

--- 60 unchanged lines hidden (view full) ---

585 const VecElem& readVecElemFlat(const RegIndex& id,
586 const ElemIndex& elemIndex) const
587 { return actualTC->readVecElemFlat(id, elemIndex); }
588
589 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
590 const VecElem& val)
591 { actualTC->setVecElemFlat(id, elemIndex, val); }
592
593 CCReg readCCRegFlat(int idx)
594 { return actualTC->readCCRegFlat(idx); }
595
596 void setCCRegFlat(int idx, CCReg val)
597 { actualTC->setCCRegFlat(idx, val); }
598};
599
600/** @{ */

--- 28 unchanged lines hidden ---