1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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76 }
77}
78
79/**
80 * ThreadContext is the external interface to all thread state for
81 * anything outside of the CPU. It provides all accessor methods to
82 * state that might be needed by external objects, ranging from
83 * register values to things such as kernel stats. It is an abstract
84 * base class; the CPU can create its own ThreadContext by
85 * deriving from it.
86 *
87 * The ThreadContext is slightly different than the ExecContext. The
88 * ThreadContext provides access to an individual thread's state; an
89 * ExecContext provides ISA access to the CPU (meaning it is
90 * implicitly multithreaded on SMT systems). Additionally the
91 * ThreadState is an abstract class that exactly defines the
92 * interface; the ExecContext is a more implicit interface that must
93 * be implemented so that the ISA can access whatever state it needs.

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129 virtual int cpuId() const = 0;
130
131 virtual uint32_t socketId() const = 0;
132
133 virtual int threadId() const = 0;
134
135 virtual void setThreadId(int id) = 0;
136
137 virtual ContextID contextId() const = 0;
138
139 virtual void setContextId(ContextID id) = 0;
140
141 virtual BaseTLB *getITBPtr() = 0;
142
143 virtual BaseTLB *getDTBPtr() = 0;
144
145 virtual CheckerCPU *getCheckerCpuPtr() = 0;
146
147 virtual TheISA::ISA *getIsaPtr() = 0;

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207
208 virtual void copyArchRegs(ThreadContext *tc) = 0;
209
210 virtual void clearArchRegs() = 0;
211
212 //
213 // New accessors for new decoder.
214 //
215 virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
216
217 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
218
219 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
220 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
221
222 /** Vector Register Lane Interfaces. */
223 /** @{ */
224 /** Reads source vector 8bit operand. */
225 virtual ConstVecLane8

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249 /** @} */
250
251 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
252
253 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
254 const = 0;
255 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
256
257 virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
258
259 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
260
261 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
262
263 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
264
265 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
266
267 virtual void setVecPredReg(const RegId& reg,
268 const VecPredRegContainer& val) = 0;
269
270 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
271
272 virtual TheISA::PCState pcState() const = 0;
273
274 virtual void pcState(const TheISA::PCState &val) = 0;
275
276 void
277 setNPC(Addr val)
278 {
279 TheISA::PCState pc_state = pcState();
280 pc_state.setNPC(val);
281 pcState(pc_state);
282 }
283
284 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
285
286 virtual Addr instAddr() const = 0;
287
288 virtual Addr nextInstAddr() const = 0;
289
290 virtual MicroPC microPC() const = 0;
291
292 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
293
294 virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
295
296 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
297
298 virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
299
300 virtual RegId flattenRegId(const RegId& regId) const = 0;
301
302 virtual RegVal
303 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
304 {
305 return 0;
306 }
307
308 virtual void
309 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
310 {
311 }
312
313 // Also not necessarily the best location for these two. Hopefully will go
314 // away once we decide upon where st cond failures goes.
315 virtual unsigned readStCondFailures() const = 0;
316
317 virtual void setStCondFailures(unsigned sc_failures) = 0;
318
319 // Same with st cond failures.
320 virtual Counter readFuncExeInst() const = 0;
321
322 virtual void syscall(int64_t callnum, Fault *fault) = 0;
323
324 // This function exits the thread context in the CPU and returns
325 // 1 if the CPU has no more active threads (meaning it's OK to exit);
326 // Used in syscall-emulation mode when a thread calls the exit syscall.
327 virtual int exit() { return 1; };
328

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336 * Some architectures have different registers visible in
337 * different modes. Such architectures "flatten" a register (see
338 * flattenRegId()) to map it into the
339 * gem5 register file. This interface provides a flat interface to
340 * the underlying register file, which allows for example
341 * serialization code to access all registers.
342 */
343
344 virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
345 virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
346
347 virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
348 virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
349
350 virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
351 virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
352 virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
353
354 virtual const VecElem& readVecElemFlat(RegIndex idx,
355 const ElemIndex& elemIdx) const = 0;
356 virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
357 const VecElem& val) = 0;
358
359 virtual const VecPredRegContainer &
360 readVecPredRegFlat(RegIndex idx) const = 0;
361 virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
362 virtual void setVecPredRegFlat(RegIndex idx,
363 const VecPredRegContainer& val) = 0;
364
365 virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
366 virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
367 /** @} */
368
369};
370
371/** @{ */
372/**
373 * Thread context serialization helpers
374 *
375 * These helper functions provide a way to the data in a
376 * ThreadContext. They are provided as separate helper function since
377 * implementing them as members of the ThreadContext interface would
378 * be confusing when the ThreadContext is exported via a proxy.
379 */
380
381void serialize(const ThreadContext &tc, CheckpointOut &cp);
382void unserialize(ThreadContext &tc, CheckpointIn &cp);
383
384/** @} */
385
386
387/**
388 * Copy state between thread contexts in preparation for CPU handover.
389 *
390 * @note This method modifies the old thread contexts as well as the
391 * new thread context. The old thread context will have its quiesce
392 * event descheduled if it is scheduled and its status set to halted.
393 *
394 * @param new_tc Destination ThreadContext.
395 * @param old_tc Source ThreadContext.
396 */
397void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
398
399#endif