1/* |
2 * Copyright (c) 2012, 2016-2017 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 27 unchanged lines hidden (view full) --- 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#include "cpu/thread_context.hh" 45 |
46#include "arch/generic/vec_pred_reg.hh" |
47#include "arch/kernel_stats.hh" 48#include "base/logging.hh" 49#include "base/trace.hh" 50#include "config/the_isa.hh" 51#include "cpu/base.hh" 52#include "cpu/quiesce_event.hh" 53#include "debug/Context.hh" 54#include "debug/Quiesce.hh" --- 27 unchanged lines hidden (view full) --- 82 for (int i = 0; i < TheISA::NumVecRegs; ++i) { 83 RegId rid(VecRegClass, i); 84 const TheISA::VecRegContainer& t1 = one->readVecReg(rid); 85 const TheISA::VecRegContainer& t2 = two->readVecReg(rid); 86 if (t1 != t2) 87 panic("Vec reg idx %d doesn't match, one: %#x, two: %#x", 88 i, t1, t2); 89 } |
90 91 // Then loop through the predicate registers. 92 for (int i = 0; i < TheISA::NumVecPredRegs; ++i) { 93 RegId rid(VecPredRegClass, i); 94 const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid); 95 const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid); 96 if (t1 != t2) 97 panic("Pred reg idx %d doesn't match, one: %#x, two: %#x", 98 i, t1, t2); 99 } 100 |
101 for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 102 RegVal t1 = one->readMiscRegNoEffect(i); 103 RegVal t2 = two->readMiscRegNoEffect(i); 104 if (t1 != t2) 105 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 106 i, t1, t2); 107 } 108 --- 66 unchanged lines hidden (view full) --- 175 arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 176 177 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); 178 for (int i = 0; i < NumVecRegs; ++i) { 179 vecRegs[i] = tc.readVecRegFlat(i); 180 } 181 SERIALIZE_CONTAINER(vecRegs); 182 |
183 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs); 184 for (int i = 0; i < NumVecPredRegs; ++i) { 185 vecPredRegs[i] = tc.readVecPredRegFlat(i); 186 } 187 SERIALIZE_CONTAINER(vecPredRegs); 188 |
189 RegVal intRegs[NumIntRegs]; 190 for (int i = 0; i < NumIntRegs; ++i) 191 intRegs[i] = tc.readIntRegFlat(i); 192 SERIALIZE_ARRAY(intRegs, NumIntRegs); 193 194#ifdef ISA_HAS_CC_REGS 195 CCReg ccRegs[NumCCRegs]; 196 for (int i = 0; i < NumCCRegs; ++i) --- 19 unchanged lines hidden (view full) --- 216 tc.setFloatRegBitsFlat(i, floatRegs[i]); 217 218 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); 219 UNSERIALIZE_CONTAINER(vecRegs); 220 for (int i = 0; i < NumVecRegs; ++i) { 221 tc.setVecRegFlat(i, vecRegs[i]); 222 } 223 |
224 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs); 225 UNSERIALIZE_CONTAINER(vecPredRegs); 226 for (int i = 0; i < NumVecPredRegs; ++i) { 227 tc.setVecPredRegFlat(i, vecPredRegs[i]); 228 } 229 |
230 RegVal intRegs[NumIntRegs]; 231 UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 232 for (int i = 0; i < NumIntRegs; ++i) 233 tc.setIntRegFlat(i, intRegs[i]); 234 235#ifdef ISA_HAS_CC_REGS 236 CCReg ccRegs[NumCCRegs]; 237 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); --- 44 unchanged lines hidden --- |