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< * Copyright (c) 2012, 2016 ARM Limited
---
> * Copyright (c) 2012, 2016-2017 ARM Limited
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> #include "arch/generic/vec_pred_reg.hh"
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>
> // Then loop through the predicate registers.
> for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
> RegId rid(VecPredRegClass, i);
> const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
> const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
> if (t1 != t2)
> panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
> i, t1, t2);
> }
>
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> std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
> for (int i = 0; i < NumVecPredRegs; ++i) {
> vecPredRegs[i] = tc.readVecPredRegFlat(i);
> }
> SERIALIZE_CONTAINER(vecPredRegs);
>
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> std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
> UNSERIALIZE_CONTAINER(vecPredRegs);
> for (int i = 0; i < NumVecPredRegs; ++i) {
> tc.setVecPredRegFlat(i, vecPredRegs[i]);
> }
>