1/* 2 * Copyright (c) 2012 ARM Limited
| 1/* 2 * Copyright (c) 2012 ARM Limited
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| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#include "base/misc.hh" 44#include "base/trace.hh" 45#include "config/the_isa.hh" 46#include "cpu/base.hh" 47#include "cpu/quiesce_event.hh" 48#include "cpu/thread_context.hh" 49#include "debug/Context.hh" 50#include "sim/full_system.hh" 51 52void 53ThreadContext::compare(ThreadContext *one, ThreadContext *two) 54{ 55 DPRINTF(Context, "Comparing thread contexts\n"); 56 57 // First loop through the integer registers. 58 for (int i = 0; i < TheISA::NumIntRegs; ++i) { 59 TheISA::IntReg t1 = one->readIntReg(i); 60 TheISA::IntReg t2 = two->readIntReg(i); 61 if (t1 != t2) 62 panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 63 i, t1, t2); 64 } 65 66 // Then loop through the floating point registers. 67 for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 68 TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 69 TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 70 if (t1 != t2) 71 panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 72 i, t1, t2); 73 } 74 for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 75 TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 76 TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 77 if (t1 != t2) 78 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 79 i, t1, t2); 80 } 81
| 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#include "base/misc.hh" 45#include "base/trace.hh" 46#include "config/the_isa.hh" 47#include "cpu/base.hh" 48#include "cpu/quiesce_event.hh" 49#include "cpu/thread_context.hh" 50#include "debug/Context.hh" 51#include "sim/full_system.hh" 52 53void 54ThreadContext::compare(ThreadContext *one, ThreadContext *two) 55{ 56 DPRINTF(Context, "Comparing thread contexts\n"); 57 58 // First loop through the integer registers. 59 for (int i = 0; i < TheISA::NumIntRegs; ++i) { 60 TheISA::IntReg t1 = one->readIntReg(i); 61 TheISA::IntReg t2 = two->readIntReg(i); 62 if (t1 != t2) 63 panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 64 i, t1, t2); 65 } 66 67 // Then loop through the floating point registers. 68 for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 69 TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 70 TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 71 if (t1 != t2) 72 panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 73 i, t1, t2); 74 } 75 for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 76 TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 77 TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 78 if (t1 != t2) 79 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 80 i, t1, t2); 81 } 82
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| 83 // loop through the Condition Code registers. 84 for (int i = 0; i < TheISA::NumCCRegs; ++i) { 85 TheISA::CCReg t1 = one->readCCReg(i); 86 TheISA::CCReg t2 = two->readCCReg(i); 87 if (t1 != t2) 88 panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 89 i, t1, t2); 90 }
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82 if (!(one->pcState() == two->pcState())) 83 panic("PC state doesn't match."); 84 int id1 = one->cpuId(); 85 int id2 = two->cpuId(); 86 if (id1 != id2) 87 panic("CPU ids don't match, one: %d, two: %d", id1, id2); 88 89 id1 = one->contextId(); 90 id2 = two->contextId(); 91 if (id1 != id2) 92 panic("Context ids don't match, one: %d, two: %d", id1, id2); 93 94 95} 96 97void 98serialize(ThreadContext &tc, std::ostream &os) 99{ 100 using namespace TheISA; 101 102 FloatRegBits floatRegs[NumFloatRegs]; 103 for (int i = 0; i < NumFloatRegs; ++i) 104 floatRegs[i] = tc.readFloatRegBitsFlat(i); 105 // This is a bit ugly, but needed to maintain backwards 106 // compatibility. 107 arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs); 108 109 IntReg intRegs[NumIntRegs]; 110 for (int i = 0; i < NumIntRegs; ++i) 111 intRegs[i] = tc.readIntRegFlat(i); 112 SERIALIZE_ARRAY(intRegs, NumIntRegs); 113
| 91 if (!(one->pcState() == two->pcState())) 92 panic("PC state doesn't match."); 93 int id1 = one->cpuId(); 94 int id2 = two->cpuId(); 95 if (id1 != id2) 96 panic("CPU ids don't match, one: %d, two: %d", id1, id2); 97 98 id1 = one->contextId(); 99 id2 = two->contextId(); 100 if (id1 != id2) 101 panic("Context ids don't match, one: %d, two: %d", id1, id2); 102 103 104} 105 106void 107serialize(ThreadContext &tc, std::ostream &os) 108{ 109 using namespace TheISA; 110 111 FloatRegBits floatRegs[NumFloatRegs]; 112 for (int i = 0; i < NumFloatRegs; ++i) 113 floatRegs[i] = tc.readFloatRegBitsFlat(i); 114 // This is a bit ugly, but needed to maintain backwards 115 // compatibility. 116 arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs); 117 118 IntReg intRegs[NumIntRegs]; 119 for (int i = 0; i < NumIntRegs; ++i) 120 intRegs[i] = tc.readIntRegFlat(i); 121 SERIALIZE_ARRAY(intRegs, NumIntRegs); 122
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| 123#ifdef ISA_HAS_CC_REGS 124 CCReg ccRegs[NumCCRegs]; 125 for (int i = 0; i < NumCCRegs; ++i) 126 ccRegs[i] = tc.readCCRegFlat(i); 127 SERIALIZE_ARRAY(ccRegs, NumCCRegs); 128#endif 129
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114 tc.pcState().serialize(os); 115 116 // thread_num and cpu_id are deterministic from the config 117} 118 119void 120unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion) 121{ 122 using namespace TheISA; 123 124 FloatRegBits floatRegs[NumFloatRegs]; 125 // This is a bit ugly, but needed to maintain backwards 126 // compatibility. 127 arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs); 128 for (int i = 0; i < NumFloatRegs; ++i) 129 tc.setFloatRegBitsFlat(i, floatRegs[i]); 130 131 IntReg intRegs[NumIntRegs]; 132 UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 133 for (int i = 0; i < NumIntRegs; ++i) 134 tc.setIntRegFlat(i, intRegs[i]); 135
| 130 tc.pcState().serialize(os); 131 132 // thread_num and cpu_id are deterministic from the config 133} 134 135void 136unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion) 137{ 138 using namespace TheISA; 139 140 FloatRegBits floatRegs[NumFloatRegs]; 141 // This is a bit ugly, but needed to maintain backwards 142 // compatibility. 143 arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs); 144 for (int i = 0; i < NumFloatRegs; ++i) 145 tc.setFloatRegBitsFlat(i, floatRegs[i]); 146 147 IntReg intRegs[NumIntRegs]; 148 UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 149 for (int i = 0; i < NumIntRegs; ++i) 150 tc.setIntRegFlat(i, intRegs[i]); 151
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| 152#ifdef ISA_HAS_CC_REGS 153 CCReg ccRegs[NumCCRegs]; 154 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 155 for (int i = 0; i < NumCCRegs; ++i) 156 tc.setCCRegFlat(i, ccRegs[i]); 157#endif 158
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136 PCState pcState; 137 pcState.unserialize(cp, section); 138 tc.pcState(pcState); 139 140 // thread_num and cpu_id are deterministic from the config 141} 142 143void 144takeOverFrom(ThreadContext &ntc, ThreadContext &otc) 145{ 146 assert(ntc.getProcessPtr() == otc.getProcessPtr()); 147 148 ntc.setStatus(otc.status()); 149 ntc.copyArchRegs(&otc); 150 ntc.setContextId(otc.contextId()); 151 ntc.setThreadId(otc.threadId()); 152 153 if (FullSystem) { 154 assert(ntc.getSystemPtr() == otc.getSystemPtr()); 155 156 BaseCPU *ncpu(ntc.getCpuPtr()); 157 assert(ncpu); 158 EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 159 assert(oqe); 160 assert(oqe->tc == &otc); 161 162 BaseCPU *ocpu(otc.getCpuPtr()); 163 assert(ocpu); 164 EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 165 assert(nqe); 166 assert(nqe->tc == &ntc); 167 168 if (oqe->scheduled()) { 169 ncpu->schedule(nqe, oqe->when()); 170 ocpu->deschedule(oqe); 171 } 172 } 173 174 otc.setStatus(ThreadContext::Halted); 175}
| 159 PCState pcState; 160 pcState.unserialize(cp, section); 161 tc.pcState(pcState); 162 163 // thread_num and cpu_id are deterministic from the config 164} 165 166void 167takeOverFrom(ThreadContext &ntc, ThreadContext &otc) 168{ 169 assert(ntc.getProcessPtr() == otc.getProcessPtr()); 170 171 ntc.setStatus(otc.status()); 172 ntc.copyArchRegs(&otc); 173 ntc.setContextId(otc.contextId()); 174 ntc.setThreadId(otc.threadId()); 175 176 if (FullSystem) { 177 assert(ntc.getSystemPtr() == otc.getSystemPtr()); 178 179 BaseCPU *ncpu(ntc.getCpuPtr()); 180 assert(ncpu); 181 EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 182 assert(oqe); 183 assert(oqe->tc == &otc); 184 185 BaseCPU *ocpu(otc.getCpuPtr()); 186 assert(ocpu); 187 EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 188 assert(nqe); 189 assert(nqe->tc == &ntc); 190 191 if (oqe->scheduled()) { 192 ncpu->schedule(nqe, oqe->when()); 193 ocpu->deschedule(oqe); 194 } 195 } 196 197 otc.setStatus(ThreadContext::Halted); 198}
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