1/*
2 * Copyright (c) 2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "cpu/thread_context.hh"
45
46#include "arch/kernel_stats.hh"
| 1/*
2 * Copyright (c) 2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "cpu/thread_context.hh"
45
46#include "arch/kernel_stats.hh"
|
48#include "base/trace.hh"
49#include "config/the_isa.hh"
50#include "cpu/base.hh"
51#include "cpu/quiesce_event.hh"
52#include "debug/Context.hh"
53#include "debug/Quiesce.hh"
54#include "params/BaseCPU.hh"
55#include "sim/full_system.hh"
56
57void
58ThreadContext::compare(ThreadContext *one, ThreadContext *two)
59{
60 DPRINTF(Context, "Comparing thread contexts\n");
61
62 // First loop through the integer registers.
63 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
64 TheISA::IntReg t1 = one->readIntReg(i);
65 TheISA::IntReg t2 = two->readIntReg(i);
66 if (t1 != t2)
67 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
68 i, t1, t2);
69 }
70
71 // Then loop through the floating point registers.
72 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
73 TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
74 TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
75 if (t1 != t2)
76 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
77 i, t1, t2);
78 }
79
80 // Then loop through the vector registers.
81 for (int i = 0; i < TheISA::NumVecRegs; ++i) {
82 RegId rid(VecRegClass, i);
83 const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
84 const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
85 if (t1 != t2)
86 panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
87 i, t1, t2);
88 }
89 for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
90 TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
91 TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
92 if (t1 != t2)
93 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
94 i, t1, t2);
95 }
96
97 // loop through the Condition Code registers.
98 for (int i = 0; i < TheISA::NumCCRegs; ++i) {
99 TheISA::CCReg t1 = one->readCCReg(i);
100 TheISA::CCReg t2 = two->readCCReg(i);
101 if (t1 != t2)
102 panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
103 i, t1, t2);
104 }
105 if (!(one->pcState() == two->pcState()))
106 panic("PC state doesn't match.");
107 int id1 = one->cpuId();
108 int id2 = two->cpuId();
109 if (id1 != id2)
110 panic("CPU ids don't match, one: %d, two: %d", id1, id2);
111
112 const ContextID cid1 = one->contextId();
113 const ContextID cid2 = two->contextId();
114 if (cid1 != cid2)
115 panic("Context ids don't match, one: %d, two: %d", id1, id2);
116
117
118}
119
120void
121ThreadContext::quiesce()
122{
123 if (!getCpuPtr()->params()->do_quiesce)
124 return;
125
126 DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
127
128 suspend();
129 if (getKernelStats())
130 getKernelStats()->quiesce();
131}
132
133
134void
135ThreadContext::quiesceTick(Tick resume)
136{
137 BaseCPU *cpu = getCpuPtr();
138
139 if (!cpu->params()->do_quiesce)
140 return;
141
142 EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
143
144 cpu->reschedule(quiesceEvent, resume, true);
145
146 DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
147
148 suspend();
149 if (getKernelStats())
150 getKernelStats()->quiesce();
151}
152
153void
154serialize(ThreadContext &tc, CheckpointOut &cp)
155{
156 using namespace TheISA;
157
158 FloatRegBits floatRegs[NumFloatRegs];
159 for (int i = 0; i < NumFloatRegs; ++i)
160 floatRegs[i] = tc.readFloatRegBitsFlat(i);
161 // This is a bit ugly, but needed to maintain backwards
162 // compatibility.
163 arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
164
165 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
166 for (int i = 0; i < NumVecRegs; ++i) {
167 vecRegs[i] = tc.readVecRegFlat(i);
168 }
169 SERIALIZE_CONTAINER(vecRegs);
170
171 IntReg intRegs[NumIntRegs];
172 for (int i = 0; i < NumIntRegs; ++i)
173 intRegs[i] = tc.readIntRegFlat(i);
174 SERIALIZE_ARRAY(intRegs, NumIntRegs);
175
176#ifdef ISA_HAS_CC_REGS
177 CCReg ccRegs[NumCCRegs];
178 for (int i = 0; i < NumCCRegs; ++i)
179 ccRegs[i] = tc.readCCRegFlat(i);
180 SERIALIZE_ARRAY(ccRegs, NumCCRegs);
181#endif
182
183 tc.pcState().serialize(cp);
184
185 // thread_num and cpu_id are deterministic from the config
186}
187
188void
189unserialize(ThreadContext &tc, CheckpointIn &cp)
190{
191 using namespace TheISA;
192
193 FloatRegBits floatRegs[NumFloatRegs];
194 // This is a bit ugly, but needed to maintain backwards
195 // compatibility.
196 arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
197 for (int i = 0; i < NumFloatRegs; ++i)
198 tc.setFloatRegBitsFlat(i, floatRegs[i]);
199
200 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
201 UNSERIALIZE_CONTAINER(vecRegs);
202 for (int i = 0; i < NumVecRegs; ++i) {
203 tc.setVecRegFlat(i, vecRegs[i]);
204 }
205
206 IntReg intRegs[NumIntRegs];
207 UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
208 for (int i = 0; i < NumIntRegs; ++i)
209 tc.setIntRegFlat(i, intRegs[i]);
210
211#ifdef ISA_HAS_CC_REGS
212 CCReg ccRegs[NumCCRegs];
213 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
214 for (int i = 0; i < NumCCRegs; ++i)
215 tc.setCCRegFlat(i, ccRegs[i]);
216#endif
217
218 PCState pcState;
219 pcState.unserialize(cp);
220 tc.pcState(pcState);
221
222 // thread_num and cpu_id are deterministic from the config
223}
224
225void
226takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
227{
228 assert(ntc.getProcessPtr() == otc.getProcessPtr());
229
230 ntc.setStatus(otc.status());
231 ntc.copyArchRegs(&otc);
232 ntc.setContextId(otc.contextId());
233 ntc.setThreadId(otc.threadId());
234
235 if (FullSystem) {
236 assert(ntc.getSystemPtr() == otc.getSystemPtr());
237
238 BaseCPU *ncpu(ntc.getCpuPtr());
239 assert(ncpu);
240 EndQuiesceEvent *oqe(otc.getQuiesceEvent());
241 assert(oqe);
242 assert(oqe->tc == &otc);
243
244 BaseCPU *ocpu(otc.getCpuPtr());
245 assert(ocpu);
246 EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
247 assert(nqe);
248 assert(nqe->tc == &ntc);
249
250 if (oqe->scheduled()) {
251 ncpu->schedule(nqe, oqe->when());
252 ocpu->deschedule(oqe);
253 }
254 }
255
256 otc.setStatus(ThreadContext::Halted);
257}
| 48#include "base/trace.hh"
49#include "config/the_isa.hh"
50#include "cpu/base.hh"
51#include "cpu/quiesce_event.hh"
52#include "debug/Context.hh"
53#include "debug/Quiesce.hh"
54#include "params/BaseCPU.hh"
55#include "sim/full_system.hh"
56
57void
58ThreadContext::compare(ThreadContext *one, ThreadContext *two)
59{
60 DPRINTF(Context, "Comparing thread contexts\n");
61
62 // First loop through the integer registers.
63 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
64 TheISA::IntReg t1 = one->readIntReg(i);
65 TheISA::IntReg t2 = two->readIntReg(i);
66 if (t1 != t2)
67 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
68 i, t1, t2);
69 }
70
71 // Then loop through the floating point registers.
72 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
73 TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
74 TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
75 if (t1 != t2)
76 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
77 i, t1, t2);
78 }
79
80 // Then loop through the vector registers.
81 for (int i = 0; i < TheISA::NumVecRegs; ++i) {
82 RegId rid(VecRegClass, i);
83 const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
84 const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
85 if (t1 != t2)
86 panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
87 i, t1, t2);
88 }
89 for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
90 TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
91 TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
92 if (t1 != t2)
93 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
94 i, t1, t2);
95 }
96
97 // loop through the Condition Code registers.
98 for (int i = 0; i < TheISA::NumCCRegs; ++i) {
99 TheISA::CCReg t1 = one->readCCReg(i);
100 TheISA::CCReg t2 = two->readCCReg(i);
101 if (t1 != t2)
102 panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
103 i, t1, t2);
104 }
105 if (!(one->pcState() == two->pcState()))
106 panic("PC state doesn't match.");
107 int id1 = one->cpuId();
108 int id2 = two->cpuId();
109 if (id1 != id2)
110 panic("CPU ids don't match, one: %d, two: %d", id1, id2);
111
112 const ContextID cid1 = one->contextId();
113 const ContextID cid2 = two->contextId();
114 if (cid1 != cid2)
115 panic("Context ids don't match, one: %d, two: %d", id1, id2);
116
117
118}
119
120void
121ThreadContext::quiesce()
122{
123 if (!getCpuPtr()->params()->do_quiesce)
124 return;
125
126 DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
127
128 suspend();
129 if (getKernelStats())
130 getKernelStats()->quiesce();
131}
132
133
134void
135ThreadContext::quiesceTick(Tick resume)
136{
137 BaseCPU *cpu = getCpuPtr();
138
139 if (!cpu->params()->do_quiesce)
140 return;
141
142 EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
143
144 cpu->reschedule(quiesceEvent, resume, true);
145
146 DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
147
148 suspend();
149 if (getKernelStats())
150 getKernelStats()->quiesce();
151}
152
153void
154serialize(ThreadContext &tc, CheckpointOut &cp)
155{
156 using namespace TheISA;
157
158 FloatRegBits floatRegs[NumFloatRegs];
159 for (int i = 0; i < NumFloatRegs; ++i)
160 floatRegs[i] = tc.readFloatRegBitsFlat(i);
161 // This is a bit ugly, but needed to maintain backwards
162 // compatibility.
163 arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
164
165 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
166 for (int i = 0; i < NumVecRegs; ++i) {
167 vecRegs[i] = tc.readVecRegFlat(i);
168 }
169 SERIALIZE_CONTAINER(vecRegs);
170
171 IntReg intRegs[NumIntRegs];
172 for (int i = 0; i < NumIntRegs; ++i)
173 intRegs[i] = tc.readIntRegFlat(i);
174 SERIALIZE_ARRAY(intRegs, NumIntRegs);
175
176#ifdef ISA_HAS_CC_REGS
177 CCReg ccRegs[NumCCRegs];
178 for (int i = 0; i < NumCCRegs; ++i)
179 ccRegs[i] = tc.readCCRegFlat(i);
180 SERIALIZE_ARRAY(ccRegs, NumCCRegs);
181#endif
182
183 tc.pcState().serialize(cp);
184
185 // thread_num and cpu_id are deterministic from the config
186}
187
188void
189unserialize(ThreadContext &tc, CheckpointIn &cp)
190{
191 using namespace TheISA;
192
193 FloatRegBits floatRegs[NumFloatRegs];
194 // This is a bit ugly, but needed to maintain backwards
195 // compatibility.
196 arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
197 for (int i = 0; i < NumFloatRegs; ++i)
198 tc.setFloatRegBitsFlat(i, floatRegs[i]);
199
200 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
201 UNSERIALIZE_CONTAINER(vecRegs);
202 for (int i = 0; i < NumVecRegs; ++i) {
203 tc.setVecRegFlat(i, vecRegs[i]);
204 }
205
206 IntReg intRegs[NumIntRegs];
207 UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
208 for (int i = 0; i < NumIntRegs; ++i)
209 tc.setIntRegFlat(i, intRegs[i]);
210
211#ifdef ISA_HAS_CC_REGS
212 CCReg ccRegs[NumCCRegs];
213 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
214 for (int i = 0; i < NumCCRegs; ++i)
215 tc.setCCRegFlat(i, ccRegs[i]);
216#endif
217
218 PCState pcState;
219 pcState.unserialize(cp);
220 tc.pcState(pcState);
221
222 // thread_num and cpu_id are deterministic from the config
223}
224
225void
226takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
227{
228 assert(ntc.getProcessPtr() == otc.getProcessPtr());
229
230 ntc.setStatus(otc.status());
231 ntc.copyArchRegs(&otc);
232 ntc.setContextId(otc.contextId());
233 ntc.setThreadId(otc.threadId());
234
235 if (FullSystem) {
236 assert(ntc.getSystemPtr() == otc.getSystemPtr());
237
238 BaseCPU *ncpu(ntc.getCpuPtr());
239 assert(ncpu);
240 EndQuiesceEvent *oqe(otc.getQuiesceEvent());
241 assert(oqe);
242 assert(oqe->tc == &otc);
243
244 BaseCPU *ocpu(otc.getCpuPtr());
245 assert(ocpu);
246 EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
247 assert(nqe);
248 assert(nqe->tc == &ntc);
249
250 if (oqe->scheduled()) {
251 ncpu->schedule(nqe, oqe->when());
252 ocpu->deschedule(oqe);
253 }
254 }
255
256 otc.setStatus(ThreadContext::Halted);
257}
|