thread_context.cc (10934:5af8f40d8f2c) | thread_context.cc (10935:acd48ddd725f) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 74 unchanged lines hidden (view full) --- 83 // loop through the Condition Code registers. 84 for (int i = 0; i < TheISA::NumCCRegs; ++i) { 85 TheISA::CCReg t1 = one->readCCReg(i); 86 TheISA::CCReg t2 = two->readCCReg(i); 87 if (t1 != t2) 88 panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 89 i, t1, t2); 90 } | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 74 unchanged lines hidden (view full) --- 83 // loop through the Condition Code registers. 84 for (int i = 0; i < TheISA::NumCCRegs; ++i) { 85 TheISA::CCReg t1 = one->readCCReg(i); 86 TheISA::CCReg t2 = two->readCCReg(i); 87 if (t1 != t2) 88 panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 89 i, t1, t2); 90 } |
91 92 // loop through the Vector registers. 93 for (int i = 0; i < TheISA::NumVectorRegs; ++i) { 94 const TheISA::VectorReg &t1 = one->readVectorReg(i); 95 const TheISA::VectorReg &t2 = two->readVectorReg(i); 96 if (t1 != t2) 97 panic("Vector reg idx %d doesn't match", i); 98 } 99 | |
100 if (!(one->pcState() == two->pcState())) 101 panic("PC state doesn't match."); 102 int id1 = one->cpuId(); 103 int id2 = two->cpuId(); 104 if (id1 != id2) 105 panic("CPU ids don't match, one: %d, two: %d", id1, id2); 106 107 id1 = one->contextId(); --- 23 unchanged lines hidden (view full) --- 131 132#ifdef ISA_HAS_CC_REGS 133 CCReg ccRegs[NumCCRegs]; 134 for (int i = 0; i < NumCCRegs; ++i) 135 ccRegs[i] = tc.readCCRegFlat(i); 136 SERIALIZE_ARRAY(ccRegs, NumCCRegs); 137#endif 138 | 91 if (!(one->pcState() == two->pcState())) 92 panic("PC state doesn't match."); 93 int id1 = one->cpuId(); 94 int id2 = two->cpuId(); 95 if (id1 != id2) 96 panic("CPU ids don't match, one: %d, two: %d", id1, id2); 97 98 id1 = one->contextId(); --- 23 unchanged lines hidden (view full) --- 122 123#ifdef ISA_HAS_CC_REGS 124 CCReg ccRegs[NumCCRegs]; 125 for (int i = 0; i < NumCCRegs; ++i) 126 ccRegs[i] = tc.readCCRegFlat(i); 127 SERIALIZE_ARRAY(ccRegs, NumCCRegs); 128#endif 129 |
139#ifdef ISA_HAS_VECTOR_REGS 140 VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements]; 141 for (int i = 0; i < NumVectorRegs; ++i) { 142 const VectorReg &v = tc.readVectorRegFlat(i); 143 for (int j = 0; i < NumVectorRegElements; ++j) 144 vectorRegs[i * NumVectorRegElements + j] = v[j]; 145 } 146 SERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements); 147#endif 148 | |
149 tc.pcState().serialize(cp); 150 151 // thread_num and cpu_id are deterministic from the config 152} 153 154void 155unserialize(ThreadContext &tc, CheckpointIn &cp) 156{ --- 13 unchanged lines hidden (view full) --- 170 171#ifdef ISA_HAS_CC_REGS 172 CCReg ccRegs[NumCCRegs]; 173 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 174 for (int i = 0; i < NumCCRegs; ++i) 175 tc.setCCRegFlat(i, ccRegs[i]); 176#endif 177 | 130 tc.pcState().serialize(cp); 131 132 // thread_num and cpu_id are deterministic from the config 133} 134 135void 136unserialize(ThreadContext &tc, CheckpointIn &cp) 137{ --- 13 unchanged lines hidden (view full) --- 151 152#ifdef ISA_HAS_CC_REGS 153 CCReg ccRegs[NumCCRegs]; 154 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 155 for (int i = 0; i < NumCCRegs; ++i) 156 tc.setCCRegFlat(i, ccRegs[i]); 157#endif 158 |
178#ifdef ISA_HAS_VECTOR_REGS 179 VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements]; 180 UNSERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements); 181 for (int i = 0; i < NumVectorRegs; ++i) { 182 VectorReg v; 183 for (int j = 0; i < NumVectorRegElements; ++j) 184 v[j] = vectorRegs[i * NumVectorRegElements + j]; 185 tc.setVectorRegFlat(i, v); 186 } 187#endif 188 | |
189 PCState pcState; 190 pcState.unserialize(cp); 191 tc.pcState(pcState); 192 193 // thread_num and cpu_id are deterministic from the config 194} 195 196void --- 32 unchanged lines hidden --- | 159 PCState pcState; 160 pcState.unserialize(cp); 161 tc.pcState(pcState); 162 163 // thread_num and cpu_id are deterministic from the config 164} 165 166void --- 32 unchanged lines hidden --- |