1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/misc.hh"
44#include "base/trace.hh"
45#include "config/the_isa.hh"
46#include "cpu/base.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Context.hh"
50#include "sim/full_system.hh"
51
52void
53ThreadContext::compare(ThreadContext *one, ThreadContext *two)
54{
55 DPRINTF(Context, "Comparing thread contexts\n");
56
57 // First loop through the integer registers.
58 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
59 TheISA::IntReg t1 = one->readIntReg(i);
60 TheISA::IntReg t2 = two->readIntReg(i);
61 if (t1 != t2)
62 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
63 i, t1, t2);
64 }
65
66 // Then loop through the floating point registers.
67 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
68 TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
69 TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
70 if (t1 != t2)
71 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
72 i, t1, t2);
73 }
74 for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
75 TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
76 TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
77 if (t1 != t2)
78 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
79 i, t1, t2);
80 }
81
82 if (!(one->pcState() == two->pcState()))
83 panic("PC state doesn't match.");
84 int id1 = one->cpuId();
85 int id2 = two->cpuId();
86 if (id1 != id2)
87 panic("CPU ids don't match, one: %d, two: %d", id1, id2);
88
89 id1 = one->contextId();
90 id2 = two->contextId();
91 if (id1 != id2)
92 panic("Context ids don't match, one: %d, two: %d", id1, id2);
93
94
95}
96
97void
98serialize(ThreadContext &tc, std::ostream &os)
99{
100 using namespace TheISA;
101
102 FloatRegBits floatRegs[NumFloatRegs];
103 for (int i = 0; i < NumFloatRegs; ++i)
104 floatRegs[i] = tc.readFloatRegBitsFlat(i);
105 // This is a bit ugly, but needed to maintain backwards
106 // compatibility.
107 arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs);
108
109 IntReg intRegs[NumIntRegs];
110 for (int i = 0; i < NumIntRegs; ++i)
111 intRegs[i] = tc.readIntRegFlat(i);
112 SERIALIZE_ARRAY(intRegs, NumIntRegs);
113
114 tc.pcState().serialize(os);
115
116 // thread_num and cpu_id are deterministic from the config
117}
118
119void
120unserialize(ThreadContext &tc, Checkpoint *cp, const std::string &section)
121{
122 using namespace TheISA;
123
124 FloatRegBits floatRegs[NumFloatRegs];
125 // This is a bit ugly, but needed to maintain backwards
126 // compatibility.
127 arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs);
128 for (int i = 0; i < NumFloatRegs; ++i)
129 tc.setFloatRegBitsFlat(i, floatRegs[i]);
130
131 IntReg intRegs[NumIntRegs];
132 UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
133 for (int i = 0; i < NumIntRegs; ++i)
134 tc.setIntRegFlat(i, intRegs[i]);
135
136 PCState pcState;
137 pcState.unserialize(cp, section);
138 tc.pcState(pcState);
139
140 // thread_num and cpu_id are deterministic from the config
141}
142
143void
144takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
145{
146 assert(ntc.getProcessPtr() == otc.getProcessPtr());
147
148 ntc.setStatus(otc.status());
149 ntc.copyArchRegs(&otc);
150 ntc.setContextId(otc.contextId());
151 ntc.setThreadId(otc.threadId());
152
153 if (FullSystem) {
154 assert(ntc.getSystemPtr() == otc.getSystemPtr());
155
156 BaseCPU *ncpu(ntc.getCpuPtr());
157 assert(ncpu);
158 EndQuiesceEvent *oqe(otc.getQuiesceEvent());
159 assert(oqe);
160 assert(oqe->tc == &otc);
161
162 BaseCPU *ocpu(otc.getCpuPtr());
163 assert(ocpu);
164 EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
165 assert(nqe);
166 assert(nqe->tc == &ntc);
167
168 if (oqe->scheduled()) {
169 ncpu->schedule(nqe, oqe->when());
170 ocpu->deschedule(oqe);
171 }
172 }
173
174 otc.setStatus(ThreadContext::Halted);
175}