traffic_gen.hh (10913:38dbdeea7f1f) | traffic_gen.hh (11168:f98eb2da15a4) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 27 unchanged lines hidden (view full) --- 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 */ 41#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ 42#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ 43 | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 27 unchanged lines hidden (view full) --- 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 */ 41#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ 42#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ 43 |
44#include "base/hashmap.hh" | 44#include <unordered_map> 45 |
45#include "base/statistics.hh" 46#include "cpu/testers/traffic_gen/generators.hh" 47#include "mem/mem_object.hh" 48#include "mem/qport.hh" 49#include "params/TrafficGen.hh" 50 51/** 52 * The traffic generator is a master module that generates stimuli for --- 77 unchanged lines hidden (view full) --- 130 131 /** State transition matrix */ 132 std::vector<std::vector<double> > transitionMatrix; 133 134 /** Index of the current state */ 135 uint32_t currState; 136 137 /** Map of generator states */ | 46#include "base/statistics.hh" 47#include "cpu/testers/traffic_gen/generators.hh" 48#include "mem/mem_object.hh" 49#include "mem/qport.hh" 50#include "params/TrafficGen.hh" 51 52/** 53 * The traffic generator is a master module that generates stimuli for --- 77 unchanged lines hidden (view full) --- 131 132 /** State transition matrix */ 133 std::vector<std::vector<double> > transitionMatrix; 134 135 /** Index of the current state */ 136 uint32_t currState; 137 138 /** Map of generator states */ |
138 m5::hash_map<uint32_t, BaseGen*> states; | 139 std::unordered_map<uint32_t, BaseGen*> states; |
139 140 /** Master port specialisation for the traffic generator */ 141 class TrafficGenPort : public MasterPort 142 { 143 public: 144 145 TrafficGenPort(const std::string& name, TrafficGen& traffic_gen) 146 : MasterPort(name, &traffic_gen), trafficGen(traffic_gen) --- 46 unchanged lines hidden (view full) --- 193 194 virtual BaseMasterPort& getMasterPort(const std::string &if_name, 195 PortID idx = InvalidPortID); 196 197 void init(); 198 199 void initState(); 200 | 140 141 /** Master port specialisation for the traffic generator */ 142 class TrafficGenPort : public MasterPort 143 { 144 public: 145 146 TrafficGenPort(const std::string& name, TrafficGen& traffic_gen) 147 : MasterPort(name, &traffic_gen), trafficGen(traffic_gen) --- 46 unchanged lines hidden (view full) --- 194 195 virtual BaseMasterPort& getMasterPort(const std::string &if_name, 196 PortID idx = InvalidPortID); 197 198 void init(); 199 200 void initState(); 201 |
201 DrainState drain() M5_ATTR_OVERRIDE; | 202 DrainState drain() override; |
202 | 203 |
203 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 204 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; | 204 void serialize(CheckpointOut &cp) const override; 205 void unserialize(CheckpointIn &cp) override; |
205 206 /** Register statistics */ 207 void regStats(); 208 209}; 210 211#endif //__CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ | 206 207 /** Register statistics */ 208 void regStats(); 209 210}; 211 212#endif //__CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ |