1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 */ 41#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ 42#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ 43 44#include <unordered_map> 45 46#include "base/statistics.hh" 47#include "cpu/testers/traffic_gen/generators.hh" 48#include "mem/mem_object.hh" 49#include "mem/qport.hh" 50#include "params/TrafficGen.hh" 51 52/** 53 * The traffic generator is a master module that generates stimuli for 54 * the memory system, based on a collection of simple generator 55 * behaviours that are either probabilistic or based on traces. It can 56 * be used stand alone for creating test cases for interconnect and 57 * memory controllers, or function as a black box replacement for 58 * system components that are not yet modelled in detail, e.g. a video 59 * engine or baseband subsystem. 60 */ 61class TrafficGen : public MemObject 62{ 63 64 private: 65 66 /** 67 * Determine next state and perform the transition. 68 */ 69 void transition(); 70 71 /** 72 * Enter a new state. 73 * 74 * @param newState identifier of state to enter 75 */ 76 void enterState(uint32_t newState); 77 78 /** 79 * Parse the config file and build the state map and 80 * transition matrix. 81 */ 82 void parseConfig(); 83 84 /** 85 * Schedules event for next update and executes an update on the 86 * state graph, either performing a state transition or executing 87 * the current state, depending on the current time. 88 */ 89 void update(); 90 91 /** 92 * Receive a retry from the neighbouring port and attempt to 93 * resend the waiting packet. 94 */ 95 void recvReqRetry(); 96 97 /** Struct to represent a probabilistic transition during parsing. */ 98 struct Transition { 99 uint32_t from; 100 uint32_t to; 101 double p; 102 }; 103 104 /** 105 * The system used to determine which mode we are currently operating 106 * in. 107 */ 108 System* system; 109 110 /** 111 * MasterID used in generated requests. 112 */ 113 MasterID masterID; 114 115 /** 116 * The config file to parse. 117 */ 118 const std::string configFile; 119 120 /** 121 * Determine whether to add elasticity in the request injection, 122 * thus responding to backpressure by slowing things down. 123 */ 124 const bool elasticReq; 125 126 /** Time of next transition */ 127 Tick nextTransitionTick; 128 129 /** Time of the next packet. */ 130 Tick nextPacketTick; 131 132 /** State transition matrix */ 133 std::vector<std::vector<double> > transitionMatrix; 134 135 /** Index of the current state */ 136 uint32_t currState; 137 138 /** Map of generator states */ 139 std::unordered_map<uint32_t, BaseGen*> states; 140 141 /** Master port specialisation for the traffic generator */ 142 class TrafficGenPort : public MasterPort 143 { 144 public: 145 146 TrafficGenPort(const std::string& name, TrafficGen& traffic_gen) 147 : MasterPort(name, &traffic_gen), trafficGen(traffic_gen) 148 { } 149 150 protected: 151 152 void recvReqRetry() { trafficGen.recvReqRetry(); } 153 154 bool recvTimingResp(PacketPtr pkt); 155 156 void recvTimingSnoopReq(PacketPtr pkt) { } 157 158 void recvFunctionalSnoop(PacketPtr pkt) { } 159 160 Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 161 162 private: 163 164 TrafficGen& trafficGen; 165 166 }; 167 168 /** The instance of master port used by the traffic generator. */ 169 TrafficGenPort port; 170 171 /** Packet waiting to be sent. */ 172 PacketPtr retryPkt; 173 174 /** Tick when the stalled packet was meant to be sent. */ 175 Tick retryPktTick; 176 177 /** Event for scheduling updates */ 178 EventWrapper<TrafficGen, &TrafficGen::update> updateEvent; 179
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