1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 162 unchanged lines hidden (view full) --- 171 PacketPtr retryPkt; 172 173 /** Tick when the stalled packet was meant to be sent. */ 174 Tick retryPktTick; 175 176 /** Event for scheduling updates */ 177 EventWrapper<TrafficGen, &TrafficGen::update> updateEvent; 178 |
179 /** Count the number of generated packets. */ 180 Stats::Scalar numPackets; 181 182 /** Count the number of retries. */ 183 Stats::Scalar numRetries; 184 185 /** Count the time incurred from back-pressure. */ 186 Stats::Scalar retryTicks; --- 6 unchanged lines hidden (view full) --- 193 194 virtual BaseMasterPort& getMasterPort(const std::string &if_name, 195 PortID idx = InvalidPortID); 196 197 void init(); 198 199 void initState(); 200 |
201 DrainState drain() M5_ATTR_OVERRIDE; |
202 203 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 204 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 205 206 /** Register statistics */ 207 void regStats(); 208 209}; 210 211#endif //__CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ |