2c2
< * Copyright (c) 2012-2013, 2016-2017 ARM Limited
---
> * Copyright (c) 2012-2013, 2016-2018 ARM Limited
47,58c47
< #include "base/statistics.hh"
< #include "cpu/testers/traffic_gen/base_gen.hh"
< #include "cpu/testers/traffic_gen/dram_gen.hh"
< #include "cpu/testers/traffic_gen/dram_rot_gen.hh"
< #include "cpu/testers/traffic_gen/exit_gen.hh"
< #include "cpu/testers/traffic_gen/idle_gen.hh"
< #include "cpu/testers/traffic_gen/linear_gen.hh"
< #include "cpu/testers/traffic_gen/random_gen.hh"
< #include "cpu/testers/traffic_gen/trace_gen.hh"
< #include "mem/mem_object.hh"
< #include "mem/qport.hh"
< #include "params/TrafficGen.hh"
---
> #include "cpu/testers/traffic_gen/base.hh"
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> struct TrafficGenParams;
>
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< * the memory system, based on a collection of simple generator
< * behaviours that are either probabilistic or based on traces. It can
< * be used stand alone for creating test cases for interconnect and
< * memory controllers, or function as a black box replacement for
< * system components that are not yet modelled in detail, e.g. a video
< * engine or baseband subsystem.
---
> * the memory system, based on a collection of simple behaviours that
> * are either probabilistic or based on traces. It can be used stand
> * alone for creating test cases for interconnect and memory
> * controllers, or function as a black-box replacement for system
> * components that are not yet modelled in detail, e.g. a video engine
> * or baseband subsystem in an SoC.
> *
> * The traffic generator has a single master port that is used to send
> * requests, independent of the specific behaviour. The behaviour of
> * the traffic generator is specified in a configuration file, and this
> * file describes a state transition graph where each state is a
> * specific generator behaviour. Examples include idling, generating
> * linear address sequences, random sequences and replay of captured
> * traces. By describing these behaviours as states, it is straight
> * forward to create very complex behaviours, simply by arranging them
> * in graphs. The graph transitions can also be annotated with
> * probabilities, effectively making it a Markov Chain.
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< class TrafficGen : public MemObject
---
> class TrafficGen : public BaseTrafficGen
71,73c73
<
< private:
<
---
> private: // Params
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< * Determine next state and perform the transition.
---
> * The config file to parse.
77c77
< void transition();
---
> const std::string configFile;
78a79
> private:
80,86d80
< * Enter a new state.
< *
< * @param newState identifier of state to enter
< */
< void enterState(uint32_t newState);
<
< /**
101,104c95,98
< /**
< * Parse the config file and build the state map and
< * transition matrix.
< */
---
> /**
> * Parse the config file and build the state map and
> * transition matrix.
> */
108,110c102
< * Schedules event for next update and executes an update on the
< * state graph, either performing a state transition or executing
< * the current state, depending on the current time.
---
> * Use the transition matrix to find the next state index.
112c104
< void update();
---
> size_t nextState();
114,124d105
< /**
< * Receive a retry from the neighbouring port and attempt to
< * resend the waiting packet.
< */
< void recvReqRetry();
<
< /**
< * Method to inform the user we have made no progress.
< */
< void noProgress();
<
132,170d112
< /**
< * The system used to determine which mode we are currently operating
< * in.
< */
< System* system;
<
< /**
< * MasterID used in generated requests.
< */
< MasterID masterID;
<
< /**
< * The config file to parse.
< */
< const std::string configFile;
<
< /**
< * Determine whether to add elasticity in the request injection,
< * thus responding to backpressure by slowing things down.
< */
< const bool elasticReq;
<
< /**
< * Time to tolerate waiting for retries (not making progress),
< * until we declare things broken.
< */
< const Tick progressCheck;
<
< /**
< * Event to keep track of our progress, or lack thereof.
< */
< EventFunctionWrapper noProgressEvent;
<
< /** Time of next transition */
< Tick nextTransitionTick;
<
< /** Time of the next packet. */
< Tick nextPacketTick;
<
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< std::unordered_map<uint32_t, BaseGen*> states;
---
> std::unordered_map<uint32_t, std::shared_ptr<BaseGen>> states;
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< /** Master port specialisation for the traffic generator */
< class TrafficGenPort : public MasterPort
< {
< public:
---
> protected: // BaseTrafficGen
> std::shared_ptr<BaseGen> nextGenerator() override;
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< TrafficGenPort(const std::string& name, TrafficGen& traffic_gen)
< : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
< { }
<
< protected:
<
< void recvReqRetry() { trafficGen.recvReqRetry(); }
<
< bool recvTimingResp(PacketPtr pkt);
<
< void recvTimingSnoopReq(PacketPtr pkt) { }
<
< void recvFunctionalSnoop(PacketPtr pkt) { }
<
< Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
<
< private:
<
< TrafficGen& trafficGen;
<
< };
<
< /** The instance of master port used by the traffic generator. */
< TrafficGenPort port;
<
< /** Packet waiting to be sent. */
< PacketPtr retryPkt;
<
< /** Tick when the stalled packet was meant to be sent. */
< Tick retryPktTick;
<
< /** Event for scheduling updates */
< EventFunctionWrapper updateEvent;
<
< uint64_t numSuppressed;
<
< /** Count the number of generated packets. */
< Stats::Scalar numPackets;
<
< /** Count the number of retries. */
< Stats::Scalar numRetries;
<
< /** Count the time incurred from back-pressure. */
< Stats::Scalar retryTicks;
<
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< BaseMasterPort& getMasterPort(const std::string &if_name,
< PortID idx = InvalidPortID) override;
<
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<
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< DrainState drain() override;
<
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< /** Register statistics */
< void regStats() override;
<
< * Copyright (c) 2012-2013, 2016-2017 ARM Limited
---
> * Copyright (c) 2012-2013, 2016-2018 ARM Limited
47,58c47
< #include "base/statistics.hh"
< #include "cpu/testers/traffic_gen/base_gen.hh"
< #include "cpu/testers/traffic_gen/dram_gen.hh"
< #include "cpu/testers/traffic_gen/dram_rot_gen.hh"
< #include "cpu/testers/traffic_gen/exit_gen.hh"
< #include "cpu/testers/traffic_gen/idle_gen.hh"
< #include "cpu/testers/traffic_gen/linear_gen.hh"
< #include "cpu/testers/traffic_gen/random_gen.hh"
< #include "cpu/testers/traffic_gen/trace_gen.hh"
< #include "mem/mem_object.hh"
< #include "mem/qport.hh"
< #include "params/TrafficGen.hh"
---
> #include "cpu/testers/traffic_gen/base.hh"
59a49,50
> struct TrafficGenParams;
>
62,67c53,69
< * the memory system, based on a collection of simple generator
< * behaviours that are either probabilistic or based on traces. It can
< * be used stand alone for creating test cases for interconnect and
< * memory controllers, or function as a black box replacement for
< * system components that are not yet modelled in detail, e.g. a video
< * engine or baseband subsystem.
---
> * the memory system, based on a collection of simple behaviours that
> * are either probabilistic or based on traces. It can be used stand
> * alone for creating test cases for interconnect and memory
> * controllers, or function as a black-box replacement for system
> * components that are not yet modelled in detail, e.g. a video engine
> * or baseband subsystem in an SoC.
> *
> * The traffic generator has a single master port that is used to send
> * requests, independent of the specific behaviour. The behaviour of
> * the traffic generator is specified in a configuration file, and this
> * file describes a state transition graph where each state is a
> * specific generator behaviour. Examples include idling, generating
> * linear address sequences, random sequences and replay of captured
> * traces. By describing these behaviours as states, it is straight
> * forward to create very complex behaviours, simply by arranging them
> * in graphs. The graph transitions can also be annotated with
> * probabilities, effectively making it a Markov Chain.
69c71
< class TrafficGen : public MemObject
---
> class TrafficGen : public BaseTrafficGen
71,73c73
<
< private:
<
---
> private: // Params
75c75
< * Determine next state and perform the transition.
---
> * The config file to parse.
77c77
< void transition();
---
> const std::string configFile;
78a79
> private:
80,86d80
< * Enter a new state.
< *
< * @param newState identifier of state to enter
< */
< void enterState(uint32_t newState);
<
< /**
101,104c95,98
< /**
< * Parse the config file and build the state map and
< * transition matrix.
< */
---
> /**
> * Parse the config file and build the state map and
> * transition matrix.
> */
108,110c102
< * Schedules event for next update and executes an update on the
< * state graph, either performing a state transition or executing
< * the current state, depending on the current time.
---
> * Use the transition matrix to find the next state index.
112c104
< void update();
---
> size_t nextState();
114,124d105
< /**
< * Receive a retry from the neighbouring port and attempt to
< * resend the waiting packet.
< */
< void recvReqRetry();
<
< /**
< * Method to inform the user we have made no progress.
< */
< void noProgress();
<
132,170d112
< /**
< * The system used to determine which mode we are currently operating
< * in.
< */
< System* system;
<
< /**
< * MasterID used in generated requests.
< */
< MasterID masterID;
<
< /**
< * The config file to parse.
< */
< const std::string configFile;
<
< /**
< * Determine whether to add elasticity in the request injection,
< * thus responding to backpressure by slowing things down.
< */
< const bool elasticReq;
<
< /**
< * Time to tolerate waiting for retries (not making progress),
< * until we declare things broken.
< */
< const Tick progressCheck;
<
< /**
< * Event to keep track of our progress, or lack thereof.
< */
< EventFunctionWrapper noProgressEvent;
<
< /** Time of next transition */
< Tick nextTransitionTick;
<
< /** Time of the next packet. */
< Tick nextPacketTick;
<
178c120
< std::unordered_map<uint32_t, BaseGen*> states;
---
> std::unordered_map<uint32_t, std::shared_ptr<BaseGen>> states;
180,183c122,123
< /** Master port specialisation for the traffic generator */
< class TrafficGenPort : public MasterPort
< {
< public:
---
> protected: // BaseTrafficGen
> std::shared_ptr<BaseGen> nextGenerator() override;
185,229d124
< TrafficGenPort(const std::string& name, TrafficGen& traffic_gen)
< : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
< { }
<
< protected:
<
< void recvReqRetry() { trafficGen.recvReqRetry(); }
<
< bool recvTimingResp(PacketPtr pkt);
<
< void recvTimingSnoopReq(PacketPtr pkt) { }
<
< void recvFunctionalSnoop(PacketPtr pkt) { }
<
< Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
<
< private:
<
< TrafficGen& trafficGen;
<
< };
<
< /** The instance of master port used by the traffic generator. */
< TrafficGenPort port;
<
< /** Packet waiting to be sent. */
< PacketPtr retryPkt;
<
< /** Tick when the stalled packet was meant to be sent. */
< Tick retryPktTick;
<
< /** Event for scheduling updates */
< EventFunctionWrapper updateEvent;
<
< uint64_t numSuppressed;
<
< /** Count the number of generated packets. */
< Stats::Scalar numPackets;
<
< /** Count the number of retries. */
< Stats::Scalar numRetries;
<
< /** Count the time incurred from back-pressure. */
< Stats::Scalar retryTicks;
<
236,238d130
< BaseMasterPort& getMasterPort(const std::string &if_name,
< PortID idx = InvalidPortID) override;
<
240d131
<
243,244d133
< DrainState drain() override;
<
248,250d136
< /** Register statistics */
< void regStats() override;
<