1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 */
41#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
42#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
43
44#include "base/hashmap.hh"
45#include "base/statistics.hh"
46#include "cpu/testers/traffic_gen/generators.hh"
47#include "mem/mem_object.hh"
48#include "mem/qport.hh"
49#include "params/TrafficGen.hh"
50
51/**
52 * The traffic generator is a master module that generates stimuli for
53 * the memory system, based on a collection of simple generator
54 * behaviours that are either probabilistic or based on traces. It can
55 * be used stand alone for creating test cases for interconnect and
56 * memory controllers, or function as a black box replacement for
57 * system components that are not yet modelled in detail, e.g. a video
58 * engine or baseband subsystem.
59 */
60class TrafficGen : public MemObject
61{
62
63 private:
64
65 /**
66 * Determine next state and perform the transition.
67 */
68 void transition();
69
70 /**
71 * Enter a new state.
72 *
73 * @param newState identifier of state to enter
74 */
75 void enterState(uint32_t newState);
76
77 /**
78 * Parse the config file and build the state map and
79 * transition matrix.
80 */
81 void parseConfig();
82
83 /**
84 * Schedules event for next update and executes an update on the
85 * state graph, either performing a state transition or executing
86 * the current state, depending on the current time.
87 */
88 void update();
89
90 /**
91 * Receive a retry from the neighbouring port and attempt to
92 * resend the waiting packet.
93 */
94 void recvReqRetry();
95
96 /** Struct to represent a probabilistic transition during parsing. */
97 struct Transition {
98 uint32_t from;
99 uint32_t to;
100 double p;
101 };
102
103 /**
104 * The system used to determine which mode we are currently operating
105 * in.
106 */
107 System* system;
108
109 /**
110 * MasterID used in generated requests.
111 */
112 MasterID masterID;
113
114 /**
115 * The config file to parse.
116 */
117 const std::string configFile;
118
119 /**
120 * Determine whether to add elasticity in the request injection,
121 * thus responding to backpressure by slowing things down.
122 */
123 const bool elasticReq;
124
125 /** Time of next transition */
126 Tick nextTransitionTick;
127
128 /** Time of the next packet. */
129 Tick nextPacketTick;
130
131 /** State transition matrix */
132 std::vector<std::vector<double> > transitionMatrix;
133
134 /** Index of the current state */
135 uint32_t currState;
136
137 /** Map of generator states */
138 m5::hash_map<uint32_t, BaseGen*> states;
139
140 /** Master port specialisation for the traffic generator */
141 class TrafficGenPort : public MasterPort
142 {
143 public:
144
145 TrafficGenPort(const std::string& name, TrafficGen& traffic_gen)
146 : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
147 { }
148
149 protected:
150
151 void recvReqRetry() { trafficGen.recvReqRetry(); }
152
153 bool recvTimingResp(PacketPtr pkt);
154
155 void recvTimingSnoopReq(PacketPtr pkt) { }
156
157 void recvFunctionalSnoop(PacketPtr pkt) { }
158
159 Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
160
161 private:
162
163 TrafficGen& trafficGen;
164
165 };
166
167 /** The instance of master port used by the traffic generator. */
168 TrafficGenPort port;
169
170 /** Packet waiting to be sent. */
171 PacketPtr retryPkt;
172
173 /** Tick when the stalled packet was meant to be sent. */
174 Tick retryPktTick;
175
176 /** Event for scheduling updates */
177 EventWrapper<TrafficGen, &TrafficGen::update> updateEvent;
178
179 /** Manager to signal when drained */
180 DrainManager* drainManager;
181
182 /** Count the number of generated packets. */
183 Stats::Scalar numPackets;
184
185 /** Count the number of retries. */
186 Stats::Scalar numRetries;
187
188 /** Count the time incurred from back-pressure. */
189 Stats::Scalar retryTicks;
190
191 public:
192
193 TrafficGen(const TrafficGenParams* p);
194
195 ~TrafficGen() {}
196
197 virtual BaseMasterPort& getMasterPort(const std::string &if_name,
198 PortID idx = InvalidPortID);
199
200 void init();
201
202 void initState();
203
204 unsigned int drain(DrainManager *dm);
205
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 */
41#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
42#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
43
44#include "base/hashmap.hh"
45#include "base/statistics.hh"
46#include "cpu/testers/traffic_gen/generators.hh"
47#include "mem/mem_object.hh"
48#include "mem/qport.hh"
49#include "params/TrafficGen.hh"
50
51/**
52 * The traffic generator is a master module that generates stimuli for
53 * the memory system, based on a collection of simple generator
54 * behaviours that are either probabilistic or based on traces. It can
55 * be used stand alone for creating test cases for interconnect and
56 * memory controllers, or function as a black box replacement for
57 * system components that are not yet modelled in detail, e.g. a video
58 * engine or baseband subsystem.
59 */
60class TrafficGen : public MemObject
61{
62
63 private:
64
65 /**
66 * Determine next state and perform the transition.
67 */
68 void transition();
69
70 /**
71 * Enter a new state.
72 *
73 * @param newState identifier of state to enter
74 */
75 void enterState(uint32_t newState);
76
77 /**
78 * Parse the config file and build the state map and
79 * transition matrix.
80 */
81 void parseConfig();
82
83 /**
84 * Schedules event for next update and executes an update on the
85 * state graph, either performing a state transition or executing
86 * the current state, depending on the current time.
87 */
88 void update();
89
90 /**
91 * Receive a retry from the neighbouring port and attempt to
92 * resend the waiting packet.
93 */
94 void recvReqRetry();
95
96 /** Struct to represent a probabilistic transition during parsing. */
97 struct Transition {
98 uint32_t from;
99 uint32_t to;
100 double p;
101 };
102
103 /**
104 * The system used to determine which mode we are currently operating
105 * in.
106 */
107 System* system;
108
109 /**
110 * MasterID used in generated requests.
111 */
112 MasterID masterID;
113
114 /**
115 * The config file to parse.
116 */
117 const std::string configFile;
118
119 /**
120 * Determine whether to add elasticity in the request injection,
121 * thus responding to backpressure by slowing things down.
122 */
123 const bool elasticReq;
124
125 /** Time of next transition */
126 Tick nextTransitionTick;
127
128 /** Time of the next packet. */
129 Tick nextPacketTick;
130
131 /** State transition matrix */
132 std::vector<std::vector<double> > transitionMatrix;
133
134 /** Index of the current state */
135 uint32_t currState;
136
137 /** Map of generator states */
138 m5::hash_map<uint32_t, BaseGen*> states;
139
140 /** Master port specialisation for the traffic generator */
141 class TrafficGenPort : public MasterPort
142 {
143 public:
144
145 TrafficGenPort(const std::string& name, TrafficGen& traffic_gen)
146 : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
147 { }
148
149 protected:
150
151 void recvReqRetry() { trafficGen.recvReqRetry(); }
152
153 bool recvTimingResp(PacketPtr pkt);
154
155 void recvTimingSnoopReq(PacketPtr pkt) { }
156
157 void recvFunctionalSnoop(PacketPtr pkt) { }
158
159 Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
160
161 private:
162
163 TrafficGen& trafficGen;
164
165 };
166
167 /** The instance of master port used by the traffic generator. */
168 TrafficGenPort port;
169
170 /** Packet waiting to be sent. */
171 PacketPtr retryPkt;
172
173 /** Tick when the stalled packet was meant to be sent. */
174 Tick retryPktTick;
175
176 /** Event for scheduling updates */
177 EventWrapper<TrafficGen, &TrafficGen::update> updateEvent;
178
179 /** Manager to signal when drained */
180 DrainManager* drainManager;
181
182 /** Count the number of generated packets. */
183 Stats::Scalar numPackets;
184
185 /** Count the number of retries. */
186 Stats::Scalar numRetries;
187
188 /** Count the time incurred from back-pressure. */
189 Stats::Scalar retryTicks;
190
191 public:
192
193 TrafficGen(const TrafficGenParams* p);
194
195 ~TrafficGen() {}
196
197 virtual BaseMasterPort& getMasterPort(const std::string &if_name,
198 PortID idx = InvalidPortID);
199
200 void init();
201
202 void initState();
203
204 unsigned int drain(DrainManager *dm);
205
|