traffic_gen.cc (12810:485ca1c27812) traffic_gen.cc (12811:269967d5b4e4)
1/*
2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * Andreas Hansson
39 * Sascha Bischoff
40 */
41#include "cpu/testers/traffic_gen/traffic_gen.hh"
42
43#include <libgen.h>
44#include <unistd.h>
45
1/*
2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * Andreas Hansson
39 * Sascha Bischoff
40 */
41#include "cpu/testers/traffic_gen/traffic_gen.hh"
42
43#include <libgen.h>
44#include <unistd.h>
45
46#include <fstream>
46#include <sstream>
47
48#include "base/intmath.hh"
49#include "base/random.hh"
47#include <sstream>
48
49#include "base/intmath.hh"
50#include "base/random.hh"
50#include "cpu/testers/traffic_gen/dram_gen.hh"
51#include "cpu/testers/traffic_gen/dram_rot_gen.hh"
52#include "cpu/testers/traffic_gen/exit_gen.hh"
53#include "cpu/testers/traffic_gen/idle_gen.hh"
54#include "cpu/testers/traffic_gen/linear_gen.hh"
55#include "cpu/testers/traffic_gen/random_gen.hh"
56#include "cpu/testers/traffic_gen/trace_gen.hh"
57#include "debug/TrafficGen.hh"
58#include "params/TrafficGen.hh"
59#include "sim/stats.hh"
60#include "sim/system.hh"
61
62using namespace std;
63
64TrafficGen::TrafficGen(const TrafficGenParams* p)

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178
179 if (mode == "TRACE") {
180 string traceFile;
181 Addr addrOffset;
182
183 is >> traceFile >> addrOffset;
184 traceFile = resolveFile(traceFile);
185
51#include "debug/TrafficGen.hh"
52#include "params/TrafficGen.hh"
53#include "sim/stats.hh"
54#include "sim/system.hh"
55
56using namespace std;
57
58TrafficGen::TrafficGen(const TrafficGenParams* p)

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172
173 if (mode == "TRACE") {
174 string traceFile;
175 Addr addrOffset;
176
177 is >> traceFile >> addrOffset;
178 traceFile = resolveFile(traceFile);
179
186 states[id].reset(new TraceGen(name(), masterID, duration,
187 traceFile, addrOffset));
180 states[id] = createTrace(duration, traceFile, addrOffset);
188 DPRINTF(TrafficGen, "State: %d TraceGen\n", id);
189 } else if (mode == "IDLE") {
181 DPRINTF(TrafficGen, "State: %d TraceGen\n", id);
182 } else if (mode == "IDLE") {
190 states[id].reset(new IdleGen(name(), masterID, duration));
183 states[id] = createIdle(duration);
191 DPRINTF(TrafficGen, "State: %d IdleGen\n", id);
192 } else if (mode == "EXIT") {
184 DPRINTF(TrafficGen, "State: %d IdleGen\n", id);
185 } else if (mode == "EXIT") {
193 states[id].reset(new ExitGen(name(), masterID, duration));
186 states[id] = createExit(duration);
194 DPRINTF(TrafficGen, "State: %d ExitGen\n", id);
195 } else if (mode == "LINEAR" || mode == "RANDOM" ||
196 mode == "DRAM" || mode == "DRAM_ROTATE") {
197 uint32_t read_percent;
198 Addr start_addr;
199 Addr end_addr;
200 Addr blocksize;
201 Tick min_period;

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206 blocksize >> min_period >> max_period >> data_limit;
207
208 DPRINTF(TrafficGen, "%s, addr %x to %x, size %d,"
209 " period %d to %d, %d%% reads\n",
210 mode, start_addr, end_addr, blocksize, min_period,
211 max_period, read_percent);
212
213
187 DPRINTF(TrafficGen, "State: %d ExitGen\n", id);
188 } else if (mode == "LINEAR" || mode == "RANDOM" ||
189 mode == "DRAM" || mode == "DRAM_ROTATE") {
190 uint32_t read_percent;
191 Addr start_addr;
192 Addr end_addr;
193 Addr blocksize;
194 Tick min_period;

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199 blocksize >> min_period >> max_period >> data_limit;
200
201 DPRINTF(TrafficGen, "%s, addr %x to %x, size %d,"
202 " period %d to %d, %d%% reads\n",
203 mode, start_addr, end_addr, blocksize, min_period,
204 max_period, read_percent);
205
206
214 if (blocksize > system->cacheLineSize())
215 fatal("TrafficGen %s block size (%d) is larger than "
216 "cache line size (%d)\n", name(),
217 blocksize, system->cacheLineSize());
218
219 if (read_percent > 100)
220 fatal("%s cannot have more than 100% reads", name());
221
222 if (min_period > max_period)
223 fatal("%s cannot have min_period > max_period", name());
224
225 if (mode == "LINEAR") {
207 if (mode == "LINEAR") {
226 states[id].reset(new LinearGen(name(), masterID,
227 duration, start_addr,
228 end_addr, blocksize,
229 min_period, max_period,
230 read_percent, data_limit));
208 states[id] = createLinear(duration, start_addr,
209 end_addr, blocksize,
210 min_period, max_period,
211 read_percent, data_limit);
231 DPRINTF(TrafficGen, "State: %d LinearGen\n", id);
232 } else if (mode == "RANDOM") {
212 DPRINTF(TrafficGen, "State: %d LinearGen\n", id);
213 } else if (mode == "RANDOM") {
233 states[id].reset(new RandomGen(name(), masterID,
234 duration, start_addr,
235 end_addr, blocksize,
236 min_period, max_period,
237 read_percent, data_limit));
214 states[id] = createRandom(duration, start_addr,
215 end_addr, blocksize,
216 min_period, max_period,
217 read_percent, data_limit);
238 DPRINTF(TrafficGen, "State: %d RandomGen\n", id);
239 } else if (mode == "DRAM" || mode == "DRAM_ROTATE") {
240 // stride size (bytes) of the request for achieving
241 // required hit length
242 unsigned int stride_size;
243 unsigned int page_size;
244 unsigned int nbr_of_banks_DRAM;
245 unsigned int nbr_of_banks_util;

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250 nbr_of_banks_util >> addr_mapping >>
251 nbr_of_ranks;
252
253 if (stride_size > page_size)
254 warn("DRAM generator stride size (%d) is greater "
255 "than page size (%d) of the memory\n",
256 blocksize, page_size);
257
218 DPRINTF(TrafficGen, "State: %d RandomGen\n", id);
219 } else if (mode == "DRAM" || mode == "DRAM_ROTATE") {
220 // stride size (bytes) of the request for achieving
221 // required hit length
222 unsigned int stride_size;
223 unsigned int page_size;
224 unsigned int nbr_of_banks_DRAM;
225 unsigned int nbr_of_banks_util;

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230 nbr_of_banks_util >> addr_mapping >>
231 nbr_of_ranks;
232
233 if (stride_size > page_size)
234 warn("DRAM generator stride size (%d) is greater "
235 "than page size (%d) of the memory\n",
236 blocksize, page_size);
237
258 if (nbr_of_banks_util > nbr_of_banks_DRAM)
259 fatal("Attempting to use more banks (%d) than "
260 "what is available (%d)\n",
261 nbr_of_banks_util, nbr_of_banks_DRAM);
262
263 // count the number of sequential packets to
264 // generate
265 unsigned int num_seq_pkts = 1;
266
267 if (stride_size > blocksize) {
268 num_seq_pkts = divCeil(stride_size, blocksize);
269 DPRINTF(TrafficGen, "stride size: %d "
270 "block size: %d, num_seq_pkts: %d\n",
271 stride_size, blocksize, num_seq_pkts);
272 }
273
274 if (mode == "DRAM") {
238 // count the number of sequential packets to
239 // generate
240 unsigned int num_seq_pkts = 1;
241
242 if (stride_size > blocksize) {
243 num_seq_pkts = divCeil(stride_size, blocksize);
244 DPRINTF(TrafficGen, "stride size: %d "
245 "block size: %d, num_seq_pkts: %d\n",
246 stride_size, blocksize, num_seq_pkts);
247 }
248
249 if (mode == "DRAM") {
275 states[id].reset(new DramGen(name(), masterID,
276 duration, start_addr,
277 end_addr, blocksize,
278 min_period, max_period,
279 read_percent, data_limit,
280 num_seq_pkts, page_size,
281 nbr_of_banks_DRAM,
282 nbr_of_banks_util,
283 addr_mapping,
284 nbr_of_ranks));
250 states[id] = createDram(duration, start_addr,
251 end_addr, blocksize,
252 min_period, max_period,
253 read_percent, data_limit,
254 num_seq_pkts, page_size,
255 nbr_of_banks_DRAM,
256 nbr_of_banks_util,
257 addr_mapping,
258 nbr_of_ranks);
285 DPRINTF(TrafficGen, "State: %d DramGen\n", id);
286 } else {
287 // Will rotate to the next rank after rotating
288 // through all banks, for each command type.
289 // In the 50% read case, series will be issued
290 // for both RD & WR before the rank in incremented
291 unsigned int max_seq_count_per_rank =
292 (read_percent == 50) ? nbr_of_banks_util * 2
293 : nbr_of_banks_util;
294
259 DPRINTF(TrafficGen, "State: %d DramGen\n", id);
260 } else {
261 // Will rotate to the next rank after rotating
262 // through all banks, for each command type.
263 // In the 50% read case, series will be issued
264 // for both RD & WR before the rank in incremented
265 unsigned int max_seq_count_per_rank =
266 (read_percent == 50) ? nbr_of_banks_util * 2
267 : nbr_of_banks_util;
268
295 states[id].reset(new DramRotGen(name(), masterID,
296 duration, start_addr,
297 end_addr, blocksize,
298 min_period, max_period,
299 read_percent, data_limit,
300 num_seq_pkts, page_size,
301 nbr_of_banks_DRAM,
302 nbr_of_banks_util,
303 addr_mapping,
304 nbr_of_ranks,
305 max_seq_count_per_rank));
269 states[id] = createDramRot(duration, start_addr,
270 end_addr, blocksize,
271 min_period, max_period,
272 read_percent,
273 data_limit,
274 num_seq_pkts, page_size,
275 nbr_of_banks_DRAM,
276 nbr_of_banks_util,
277 addr_mapping,
278 nbr_of_ranks,
279 max_seq_count_per_rank);
306 DPRINTF(TrafficGen, "State: %d DramRotGen\n", id);
307 }
308 }
309 } else {
310 fatal("%s: Unknown traffic generator mode: %s",
311 name(), mode);
312 }
313 } else if (keyword == "TRANSITION") {

--- 78 unchanged lines hidden --- 		280 DPRINTF(TrafficGen, "State: %d DramRotGen\n", id);
281 }
282 }
283 } else {
284 fatal("%s: Unknown traffic generator mode: %s",
285 name(), mode);
286 }
287 } else if (keyword == "TRANSITION") {

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