traffic_gen.cc (10128:013bba88efab) | traffic_gen.cc (10138:0e40c53fe85c) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 27 unchanged lines hidden (view full) --- 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 */ 41 42#include <sstream> 43 | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 27 unchanged lines hidden (view full) --- 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 */ 41 42#include <sstream> 43 |
44#include "base/intmath.hh" |
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44#include "base/random.hh" 45#include "cpu/testers/traffic_gen/traffic_gen.hh" 46#include "debug/Checkpoint.hh" 47#include "debug/TrafficGen.hh" 48#include "sim/stats.hh" 49#include "sim/system.hh" 50 51using namespace std; --- 200 unchanged lines hidden (view full) --- 252 is >> traceFile >> addrOffset; 253 254 states[id] = new TraceGen(name(), masterID, duration, 255 traceFile, addrOffset); 256 DPRINTF(TrafficGen, "State: %d TraceGen\n", id); 257 } else if (mode == "IDLE") { 258 states[id] = new IdleGen(name(), masterID, duration); 259 DPRINTF(TrafficGen, "State: %d IdleGen\n", id); | 45#include "base/random.hh" 46#include "cpu/testers/traffic_gen/traffic_gen.hh" 47#include "debug/Checkpoint.hh" 48#include "debug/TrafficGen.hh" 49#include "sim/stats.hh" 50#include "sim/system.hh" 51 52using namespace std; --- 200 unchanged lines hidden (view full) --- 253 is >> traceFile >> addrOffset; 254 255 states[id] = new TraceGen(name(), masterID, duration, 256 traceFile, addrOffset); 257 DPRINTF(TrafficGen, "State: %d TraceGen\n", id); 258 } else if (mode == "IDLE") { 259 states[id] = new IdleGen(name(), masterID, duration); 260 DPRINTF(TrafficGen, "State: %d IdleGen\n", id); |
260 } else if (mode == "LINEAR" || mode == "RANDOM") { | 261 } else if (mode == "LINEAR" || mode == "RANDOM" || 262 mode == "DRAM") { |
261 uint32_t read_percent; 262 Addr start_addr; 263 Addr end_addr; 264 Addr blocksize; 265 Tick min_period; 266 Tick max_period; 267 Addr data_limit; 268 269 is >> read_percent >> start_addr >> end_addr >> 270 blocksize >> min_period >> max_period >> data_limit; 271 272 DPRINTF(TrafficGen, "%s, addr %x to %x, size %d," 273 " period %d to %d, %d%% reads\n", 274 mode, start_addr, end_addr, blocksize, min_period, 275 max_period, read_percent); 276 277 278 if (blocksize > system->cacheLineSize()) 279 fatal("TrafficGen %s block size (%d) is larger than " | 263 uint32_t read_percent; 264 Addr start_addr; 265 Addr end_addr; 266 Addr blocksize; 267 Tick min_period; 268 Tick max_period; 269 Addr data_limit; 270 271 is >> read_percent >> start_addr >> end_addr >> 272 blocksize >> min_period >> max_period >> data_limit; 273 274 DPRINTF(TrafficGen, "%s, addr %x to %x, size %d," 275 " period %d to %d, %d%% reads\n", 276 mode, start_addr, end_addr, blocksize, min_period, 277 max_period, read_percent); 278 279 280 if (blocksize > system->cacheLineSize()) 281 fatal("TrafficGen %s block size (%d) is larger than " |
280 "system block size (%d)\n", name(), | 282 "cache line size (%d)\n", name(), |
281 blocksize, system->cacheLineSize()); 282 283 if (read_percent > 100) 284 fatal("%s cannot have more than 100% reads", name()); 285 286 if (min_period > max_period) 287 fatal("%s cannot have min_period > max_period", name()); 288 --- 6 unchanged lines hidden (view full) --- 295 DPRINTF(TrafficGen, "State: %d LinearGen\n", id); 296 } else if (mode == "RANDOM") { 297 states[id] = new RandomGen(name(), masterID, 298 duration, start_addr, 299 end_addr, blocksize, 300 min_period, max_period, 301 read_percent, data_limit); 302 DPRINTF(TrafficGen, "State: %d RandomGen\n", id); | 283 blocksize, system->cacheLineSize()); 284 285 if (read_percent > 100) 286 fatal("%s cannot have more than 100% reads", name()); 287 288 if (min_period > max_period) 289 fatal("%s cannot have min_period > max_period", name()); 290 --- 6 unchanged lines hidden (view full) --- 297 DPRINTF(TrafficGen, "State: %d LinearGen\n", id); 298 } else if (mode == "RANDOM") { 299 states[id] = new RandomGen(name(), masterID, 300 duration, start_addr, 301 end_addr, blocksize, 302 min_period, max_period, 303 read_percent, data_limit); 304 DPRINTF(TrafficGen, "State: %d RandomGen\n", id); |
305 } else if (mode == "DRAM") { 306 // stride size (bytes) of the request for achieving 307 // required hit length 308 unsigned int stride_size; 309 unsigned int page_size; 310 unsigned int nbr_of_banks_DRAM; 311 unsigned int nbr_of_banks_util; 312 unsigned int addr_mapping; 313 314 is >> stride_size >> page_size >> nbr_of_banks_DRAM >> 315 nbr_of_banks_util >> addr_mapping; 316 317 if (stride_size > page_size) 318 warn("DRAM generator stride size (%d) is greater " 319 "than page size (%d) of the memory\n", 320 blocksize, page_size); 321 322 if (nbr_of_banks_util > nbr_of_banks_DRAM) 323 fatal("Attempting to use more banks (%) than " 324 "what is available (%)\n", 325 nbr_of_banks_util, nbr_of_banks_DRAM); 326 327 if (nbr_of_banks_util > nbr_of_banks_DRAM) 328 fatal("Attempting to use more banks (%) than " 329 "what is available (%)\n", 330 nbr_of_banks_util, nbr_of_banks_DRAM); 331 332 // count the number of sequential packets to 333 // generate 334 unsigned int num_seq_pkts = 1; 335 336 if (stride_size > blocksize) { 337 num_seq_pkts = divCeil(stride_size, blocksize); 338 DPRINTF(TrafficGen, "stride size: %d " 339 "block size: %d, num_seq_pkts: %d\n", 340 stride_size, blocksize, num_seq_pkts); 341 } 342 343 states[id] = new DramGen(name(), masterID, 344 duration, start_addr, 345 end_addr, blocksize, 346 min_period, max_period, 347 read_percent, data_limit, 348 num_seq_pkts, page_size, 349 nbr_of_banks_DRAM, 350 nbr_of_banks_util, 351 addr_mapping); 352 DPRINTF(TrafficGen, "State: %d DramGen\n", id); |
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303 } 304 } else { 305 fatal("%s: Unknown traffic generator mode: %s", 306 name(), mode); 307 } 308 } else if (keyword == "TRANSITION") { 309 Transition transition; 310 --- 144 unchanged lines hidden --- | 353 } 354 } else { 355 fatal("%s: Unknown traffic generator mode: %s", 356 name(), mode); 357 } 358 } else if (keyword == "TRANSITION") { 359 Transition transition; 360 --- 144 unchanged lines hidden --- |