1/* 2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 * Andreas Hansson 39 * Sascha Bischoff 40 */ 41#include "cpu/testers/traffic_gen/traffic_gen.hh" 42 43#include <libgen.h> 44#include <unistd.h> 45 |
46#include <fstream> |
47#include <sstream> 48 49#include "base/intmath.hh" 50#include "base/random.hh" |
51#include "debug/TrafficGen.hh" 52#include "params/TrafficGen.hh" 53#include "sim/stats.hh" 54#include "sim/system.hh" 55 56using namespace std; 57 58TrafficGen::TrafficGen(const TrafficGenParams* p) --- 113 unchanged lines hidden (view full) --- 172 173 if (mode == "TRACE") { 174 string traceFile; 175 Addr addrOffset; 176 177 is >> traceFile >> addrOffset; 178 traceFile = resolveFile(traceFile); 179 |
180 states[id] = createTrace(duration, traceFile, addrOffset); |
181 DPRINTF(TrafficGen, "State: %d TraceGen\n", id); 182 } else if (mode == "IDLE") { |
183 states[id] = createIdle(duration); |
184 DPRINTF(TrafficGen, "State: %d IdleGen\n", id); 185 } else if (mode == "EXIT") { |
186 states[id] = createExit(duration); |
187 DPRINTF(TrafficGen, "State: %d ExitGen\n", id); 188 } else if (mode == "LINEAR" || mode == "RANDOM" || 189 mode == "DRAM" || mode == "DRAM_ROTATE") { 190 uint32_t read_percent; 191 Addr start_addr; 192 Addr end_addr; 193 Addr blocksize; 194 Tick min_period; --- 4 unchanged lines hidden (view full) --- 199 blocksize >> min_period >> max_period >> data_limit; 200 201 DPRINTF(TrafficGen, "%s, addr %x to %x, size %d," 202 " period %d to %d, %d%% reads\n", 203 mode, start_addr, end_addr, blocksize, min_period, 204 max_period, read_percent); 205 206 |
207 if (mode == "LINEAR") { |
208 states[id] = createLinear(duration, start_addr, 209 end_addr, blocksize, 210 min_period, max_period, 211 read_percent, data_limit); |
212 DPRINTF(TrafficGen, "State: %d LinearGen\n", id); 213 } else if (mode == "RANDOM") { |
214 states[id] = createRandom(duration, start_addr, 215 end_addr, blocksize, 216 min_period, max_period, 217 read_percent, data_limit); |
218 DPRINTF(TrafficGen, "State: %d RandomGen\n", id); 219 } else if (mode == "DRAM" || mode == "DRAM_ROTATE") { 220 // stride size (bytes) of the request for achieving 221 // required hit length 222 unsigned int stride_size; 223 unsigned int page_size; 224 unsigned int nbr_of_banks_DRAM; 225 unsigned int nbr_of_banks_util; --- 4 unchanged lines hidden (view full) --- 230 nbr_of_banks_util >> addr_mapping >> 231 nbr_of_ranks; 232 233 if (stride_size > page_size) 234 warn("DRAM generator stride size (%d) is greater " 235 "than page size (%d) of the memory\n", 236 blocksize, page_size); 237 |
238 // count the number of sequential packets to 239 // generate 240 unsigned int num_seq_pkts = 1; 241 242 if (stride_size > blocksize) { 243 num_seq_pkts = divCeil(stride_size, blocksize); 244 DPRINTF(TrafficGen, "stride size: %d " 245 "block size: %d, num_seq_pkts: %d\n", 246 stride_size, blocksize, num_seq_pkts); 247 } 248 249 if (mode == "DRAM") { |
250 states[id] = createDram(duration, start_addr, 251 end_addr, blocksize, 252 min_period, max_period, 253 read_percent, data_limit, 254 num_seq_pkts, page_size, 255 nbr_of_banks_DRAM, 256 nbr_of_banks_util, 257 addr_mapping, 258 nbr_of_ranks); |
259 DPRINTF(TrafficGen, "State: %d DramGen\n", id); 260 } else { 261 // Will rotate to the next rank after rotating 262 // through all banks, for each command type. 263 // In the 50% read case, series will be issued 264 // for both RD & WR before the rank in incremented 265 unsigned int max_seq_count_per_rank = 266 (read_percent == 50) ? nbr_of_banks_util * 2 267 : nbr_of_banks_util; 268 |
269 states[id] = createDramRot(duration, start_addr, 270 end_addr, blocksize, 271 min_period, max_period, 272 read_percent, 273 data_limit, 274 num_seq_pkts, page_size, 275 nbr_of_banks_DRAM, 276 nbr_of_banks_util, 277 addr_mapping, 278 nbr_of_ranks, 279 max_seq_count_per_rank); |
280 DPRINTF(TrafficGen, "State: %d DramRotGen\n", id); 281 } 282 } 283 } else { 284 fatal("%s: Unknown traffic generator mode: %s", 285 name(), mode); 286 } 287 } else if (keyword == "TRANSITION") { --- 78 unchanged lines hidden --- |