1/* |
2 * Copyright (c) 2012-2013, 2016-2017 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 289 unchanged lines hidden (view full) --- 300 traceFile = resolveFile(traceFile); 301 302 states[id] = new TraceGen(name(), masterID, duration, 303 traceFile, addrOffset); 304 DPRINTF(TrafficGen, "State: %d TraceGen\n", id); 305 } else if (mode == "IDLE") { 306 states[id] = new IdleGen(name(), masterID, duration); 307 DPRINTF(TrafficGen, "State: %d IdleGen\n", id); |
308 } else if (mode == "EXIT") { 309 states[id] = new ExitGen(name(), masterID, duration); 310 DPRINTF(TrafficGen, "State: %d ExitGen\n", id); |
311 } else if (mode == "LINEAR" || mode == "RANDOM" || 312 mode == "DRAM" || mode == "DRAM_ROTATE") { 313 uint32_t read_percent; 314 Addr start_addr; 315 Addr end_addr; 316 Addr blocksize; 317 Tick min_period; 318 Tick max_period; --- 264 unchanged lines hidden --- |