1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 */
41
42#include <sstream>
43
44#include "base/random.hh"
45#include "cpu/testers/traffic_gen/traffic_gen.hh"
46#include "debug/Checkpoint.hh"
47#include "debug/TrafficGen.hh"
48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53TrafficGen::TrafficGen(const TrafficGenParams* p)
54 : MemObject(p),
55 system(p->system),

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338{
339 DPRINTF(TrafficGen, "Transition to state %d\n", newState);
340
341 currState = newState;
342 nextTransitionTick += states[currState]->duration;
343 states[currState]->enter();
344}
345
346bool
347TrafficGen::TrafficGenPort::recvTimingResp(PacketPtr pkt)
348{
349 delete pkt->req;
350 delete pkt;
351
352 return true;
353}