1/* 2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 57 unchanged lines hidden (view full) --- 66 67 public: 68 69 /** 70 * Create a linear address sequence generator. Set 71 * min_period == max_period for a fixed inter-transaction 72 * time. 73 * |
74 * @param obj SimObject owning this sequence generator 75 * @param master_id MasterID related to the memory requests |
76 * @param _duration duration of this state before transitioning 77 * @param start_addr Start address 78 * @param end_addr End address 79 * @param _blocksize Size used for transactions injected |
80 * @param cacheline_size cache line size in the system |
81 * @param min_period Lower limit of random inter-transaction time 82 * @param max_period Upper limit of random inter-transaction time 83 * @param read_percent Percent of transactions that are reads 84 * @param data_limit Upper limit on how much data to read/write 85 */ |
86 LinearGen(SimObject &obj, 87 MasterID master_id, Tick _duration, 88 Addr start_addr, Addr end_addr, 89 Addr _blocksize, Addr cacheline_size, |
90 Tick min_period, Tick max_period, 91 uint8_t read_percent, Addr data_limit) |
92 : StochasticGen(obj, master_id, _duration, start_addr, end_addr, 93 _blocksize, cacheline_size, min_period, max_period, 94 read_percent, data_limit), |
95 nextAddr(0), 96 dataManipulated(0) 97 { } 98 99 void enter(); 100 101 PacketPtr getNextPacket(); 102 --- 15 unchanged lines hidden --- |