1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 * Neha Agarwal
41 */
42
43/**
44 * @file
45 * Declaration of the linear generator that generates sequential
46 * requests.
47 */
48
49#ifndef __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__
50#define __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__
51
52#include "base/bitfield.hh"
53#include "base/intmath.hh"
54#include "base_gen.hh"
55#include "mem/packet.hh"
56
57/**
58 * The linear generator generates sequential requests from a
59 * start to an end address, with a fixed block size. A
60 * fraction of the requests are reads, as determined by the
61 * read percent. There is an optional data limit for when to
62 * stop generating new requests.
63 */
64class LinearGen : public StochasticGen
65{
66
67 public:
68
69 /**
70 * Create a linear address sequence generator. Set
71 * min_period == max_period for a fixed inter-transaction
72 * time.
73 *
| 1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 * Neha Agarwal
41 */
42
43/**
44 * @file
45 * Declaration of the linear generator that generates sequential
46 * requests.
47 */
48
49#ifndef __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__
50#define __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__
51
52#include "base/bitfield.hh"
53#include "base/intmath.hh"
54#include "base_gen.hh"
55#include "mem/packet.hh"
56
57/**
58 * The linear generator generates sequential requests from a
59 * start to an end address, with a fixed block size. A
60 * fraction of the requests are reads, as determined by the
61 * read percent. There is an optional data limit for when to
62 * stop generating new requests.
63 */
64class LinearGen : public StochasticGen
65{
66
67 public:
68
69 /**
70 * Create a linear address sequence generator. Set
71 * min_period == max_period for a fixed inter-transaction
72 * time.
73 *
|
74 * @param gen Traffic generator owning this sequence generator
| 74 * @param obj SimObject owning this sequence generator
75 * @param master_id MasterID related to the memory requests
|
75 * @param _duration duration of this state before transitioning
76 * @param start_addr Start address
77 * @param end_addr End address
78 * @param _blocksize Size used for transactions injected
| 76 * @param _duration duration of this state before transitioning
77 * @param start_addr Start address
78 * @param end_addr End address
79 * @param _blocksize Size used for transactions injected
|
| 80 * @param cacheline_size cache line size in the system
|
79 * @param min_period Lower limit of random inter-transaction time
80 * @param max_period Upper limit of random inter-transaction time
81 * @param read_percent Percent of transactions that are reads
82 * @param data_limit Upper limit on how much data to read/write
83 */
| 81 * @param min_period Lower limit of random inter-transaction time
82 * @param max_period Upper limit of random inter-transaction time
83 * @param read_percent Percent of transactions that are reads
84 * @param data_limit Upper limit on how much data to read/write
85 */
|
84 LinearGen(BaseTrafficGen &gen, Tick _duration,
85 Addr start_addr, Addr end_addr, Addr _blocksize,
| 86 LinearGen(SimObject &obj,
87 MasterID master_id, Tick _duration,
88 Addr start_addr, Addr end_addr,
89 Addr _blocksize, Addr cacheline_size,
|
86 Tick min_period, Tick max_period,
87 uint8_t read_percent, Addr data_limit)
| 90 Tick min_period, Tick max_period,
91 uint8_t read_percent, Addr data_limit)
|
88 : StochasticGen(gen, _duration, start_addr, end_addr,
89 _blocksize, min_period, max_period, read_percent,
90 data_limit),
| 92 : StochasticGen(obj, master_id, _duration, start_addr, end_addr,
93 _blocksize, cacheline_size, min_period, max_period,
94 read_percent, data_limit),
|
91 nextAddr(0),
92 dataManipulated(0)
93 { }
94
95 void enter();
96
97 PacketPtr getNextPacket();
98
99 Tick nextPacketTick(bool elastic, Tick delay) const;
100
101 private:
102 /** Address of next request */
103 Addr nextAddr;
104
105 /**
106 * Counter to determine the amount of data
107 * manipulated. Used to determine if we should continue
108 * generating requests.
109 */
110 Addr dataManipulated;
111};
112
113#endif
| 95 nextAddr(0),
96 dataManipulated(0)
97 { }
98
99 void enter();
100
101 PacketPtr getNextPacket();
102
103 Tick nextPacketTick(bool elastic, Tick delay) const;
104
105 private:
106 /** Address of next request */
107 Addr nextAddr;
108
109 /**
110 * Counter to determine the amount of data
111 * manipulated. Used to determine if we should continue
112 * generating requests.
113 */
114 Addr dataManipulated;
115};
116
117#endif
|